1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright 2017 NXP 4 * Copyright 2016 Freescale Semiconductor, Inc. 5 */ 6 7#include <linux/bitfield.h> 8#include <linux/init.h> 9#include <linux/interrupt.h> 10#include <linux/io.h> 11#include <linux/module.h> 12#include <linux/of.h> 13#include <linux/of_irq.h> 14#include <linux/perf_event.h> 15#include <linux/platform_device.h> 16#include <linux/slab.h> 17 18#define COUNTER_CNTL 0x0 19#define COUNTER_READ 0x20 20 21#define COUNTER_DPCR1 0x30 22#define COUNTER_MUX_CNTL 0x50 23#define COUNTER_MASK_COMP 0x54 24 25#define CNTL_OVER 0x1 26#define CNTL_CLEAR 0x2 27#define CNTL_EN 0x4 28#define CNTL_EN_MASK 0xFFFFFFFB 29#define CNTL_CLEAR_MASK 0xFFFFFFFD 30#define CNTL_OVER_MASK 0xFFFFFFFE 31 32#define CNTL_CP_SHIFT 16 33#define CNTL_CP_MASK (0xFF << CNTL_CP_SHIFT) 34#define CNTL_CSV_SHIFT 24 35#define CNTL_CSV_MASK (0xFFU << CNTL_CSV_SHIFT) 36 37#define READ_PORT_SHIFT 0 38#define READ_PORT_MASK (0x7 << READ_PORT_SHIFT) 39#define READ_CHANNEL_REVERT 0x00000008 /* bit 3 for read channel select */ 40#define WRITE_PORT_SHIFT 8 41#define WRITE_PORT_MASK (0x7 << WRITE_PORT_SHIFT) 42#define WRITE_CHANNEL_REVERT 0x00000800 /* bit 11 for write channel select */ 43 44#define EVENT_CYCLES_ID 0 45#define EVENT_CYCLES_COUNTER 0 46#define NUM_COUNTERS 4 47 48/* For removing bias if cycle counter CNTL.CP is set to 0xf0 */ 49#define CYCLES_COUNTER_MASK 0x0FFFFFFF 50#define AXI_MASKING_REVERT 0xffff0000 /* AXI_MASKING(MSB 16bits) + AXI_ID(LSB 16bits) */ 51 52#define to_ddr_pmu(p) container_of(p, struct ddr_pmu, pmu) 53 54#define DDR_PERF_DEV_NAME "imx8_ddr" 55#define DDR_CPUHP_CB_NAME DDR_PERF_DEV_NAME "_perf_pmu" 56 57static DEFINE_IDA(ddr_ida); 58 59/* DDR Perf hardware feature */ 60#define DDR_CAP_AXI_ID_FILTER 0x1 /* support AXI ID filter */ 61#define DDR_CAP_AXI_ID_FILTER_ENHANCED 0x3 /* support enhanced AXI ID filter */ 62#define DDR_CAP_AXI_ID_PORT_CHANNEL_FILTER 0x4 /* support AXI ID PORT CHANNEL filter */ 63 64struct fsl_ddr_devtype_data { 65 unsigned int quirks; /* quirks needed for different DDR Perf core */ 66 const char *identifier; /* system PMU identifier for userspace */ 67}; 68 69static const struct fsl_ddr_devtype_data imx8_devtype_data; 70 71static const struct fsl_ddr_devtype_data imx8m_devtype_data = { 72 .quirks = DDR_CAP_AXI_ID_FILTER, 73}; 74 75static const struct fsl_ddr_devtype_data imx8mq_devtype_data = { 76 .quirks = DDR_CAP_AXI_ID_FILTER, 77 .identifier = "i.MX8MQ", 78}; 79 80static const struct fsl_ddr_devtype_data imx8mm_devtype_data = { 81 .quirks = DDR_CAP_AXI_ID_FILTER, 82 .identifier = "i.MX8MM", 83}; 84 85static const struct fsl_ddr_devtype_data imx8mn_devtype_data = { 86 .quirks = DDR_CAP_AXI_ID_FILTER, 87 .identifier = "i.MX8MN", 88}; 89 90static const struct fsl_ddr_devtype_data imx8mp_devtype_data = { 91 .quirks = DDR_CAP_AXI_ID_FILTER_ENHANCED, 92 .identifier = "i.MX8MP", 93}; 94 95static const struct fsl_ddr_devtype_data imx8dxl_devtype_data = { 96 .quirks = DDR_CAP_AXI_ID_PORT_CHANNEL_FILTER, 97 .identifier = "i.MX8DXL", 98}; 99 100static const struct of_device_id imx_ddr_pmu_dt_ids[] = { 101 { .compatible = "fsl,imx8-ddr-pmu", .data = &imx8_devtype_data}, 102 { .compatible = "fsl,imx8m-ddr-pmu", .data = &imx8m_devtype_data}, 103 { .compatible = "fsl,imx8mq-ddr-pmu", .data = &imx8mq_devtype_data}, 104 { .compatible = "fsl,imx8mm-ddr-pmu", .data = &imx8mm_devtype_data}, 105 { .compatible = "fsl,imx8mn-ddr-pmu", .data = &imx8mn_devtype_data}, 106 { .compatible = "fsl,imx8mp-ddr-pmu", .data = &imx8mp_devtype_data}, 107 { .compatible = "fsl,imx8dxl-ddr-pmu", .data = &imx8dxl_devtype_data}, 108 { /* sentinel */ } 109}; 110MODULE_DEVICE_TABLE(of, imx_ddr_pmu_dt_ids); 111 112struct ddr_pmu { 113 struct pmu pmu; 114 void __iomem *base; 115 unsigned int cpu; 116 struct hlist_node node; 117 struct device *dev; 118 struct perf_event *events[NUM_COUNTERS]; 119 enum cpuhp_state cpuhp_state; 120 const struct fsl_ddr_devtype_data *devtype_data; 121 int irq; 122 int id; 123 int active_counter; 124}; 125 126static ssize_t ddr_perf_identifier_show(struct device *dev, 127 struct device_attribute *attr, 128 char *page) 129{ 130 struct ddr_pmu *pmu = dev_get_drvdata(dev); 131 132 return sysfs_emit(page, "%s\n", pmu->devtype_data->identifier); 133} 134 135static umode_t ddr_perf_identifier_attr_visible(struct kobject *kobj, 136 struct attribute *attr, 137 int n) 138{ 139 struct device *dev = kobj_to_dev(kobj); 140 struct ddr_pmu *pmu = dev_get_drvdata(dev); 141 142 if (!pmu->devtype_data->identifier) 143 return 0; 144 return attr->mode; 145}; 146 147static struct device_attribute ddr_perf_identifier_attr = 148 __ATTR(identifier, 0444, ddr_perf_identifier_show, NULL); 149 150static struct attribute *ddr_perf_identifier_attrs[] = { 151 &ddr_perf_identifier_attr.attr, 152 NULL, 153}; 154 155static const struct attribute_group ddr_perf_identifier_attr_group = { 156 .attrs = ddr_perf_identifier_attrs, 157 .is_visible = ddr_perf_identifier_attr_visible, 158}; 159 160enum ddr_perf_filter_capabilities { 161 PERF_CAP_AXI_ID_FILTER = 0, 162 PERF_CAP_AXI_ID_FILTER_ENHANCED, 163 PERF_CAP_AXI_ID_PORT_CHANNEL_FILTER, 164 PERF_CAP_AXI_ID_FEAT_MAX, 165}; 166 167static u32 ddr_perf_filter_cap_get(struct ddr_pmu *pmu, int cap) 168{ 169 u32 quirks = pmu->devtype_data->quirks; 170 171 switch (cap) { 172 case PERF_CAP_AXI_ID_FILTER: 173 return !!(quirks & DDR_CAP_AXI_ID_FILTER); 174 case PERF_CAP_AXI_ID_FILTER_ENHANCED: 175 quirks &= DDR_CAP_AXI_ID_FILTER_ENHANCED; 176 return quirks == DDR_CAP_AXI_ID_FILTER_ENHANCED; 177 case PERF_CAP_AXI_ID_PORT_CHANNEL_FILTER: 178 return !!(quirks & DDR_CAP_AXI_ID_PORT_CHANNEL_FILTER); 179 default: 180 WARN(1, "unknown filter cap %d\n", cap); 181 } 182 183 return 0; 184} 185 186static ssize_t ddr_perf_filter_cap_show(struct device *dev, 187 struct device_attribute *attr, 188 char *buf) 189{ 190 struct ddr_pmu *pmu = dev_get_drvdata(dev); 191 struct dev_ext_attribute *ea = 192 container_of(attr, struct dev_ext_attribute, attr); 193 int cap = (long)ea->var; 194 195 return sysfs_emit(buf, "%u\n", ddr_perf_filter_cap_get(pmu, cap)); 196} 197 198#define PERF_EXT_ATTR_ENTRY(_name, _func, _var) \ 199 (&((struct dev_ext_attribute) { \ 200 __ATTR(_name, 0444, _func, NULL), (void *)_var \ 201 }).attr.attr) 202 203#define PERF_FILTER_EXT_ATTR_ENTRY(_name, _var) \ 204 PERF_EXT_ATTR_ENTRY(_name, ddr_perf_filter_cap_show, _var) 205 206static struct attribute *ddr_perf_filter_cap_attr[] = { 207 PERF_FILTER_EXT_ATTR_ENTRY(filter, PERF_CAP_AXI_ID_FILTER), 208 PERF_FILTER_EXT_ATTR_ENTRY(enhanced_filter, PERF_CAP_AXI_ID_FILTER_ENHANCED), 209 PERF_FILTER_EXT_ATTR_ENTRY(super_filter, PERF_CAP_AXI_ID_PORT_CHANNEL_FILTER), 210 NULL, 211}; 212 213static const struct attribute_group ddr_perf_filter_cap_attr_group = { 214 .name = "caps", 215 .attrs = ddr_perf_filter_cap_attr, 216}; 217 218static ssize_t ddr_perf_cpumask_show(struct device *dev, 219 struct device_attribute *attr, char *buf) 220{ 221 struct ddr_pmu *pmu = dev_get_drvdata(dev); 222 223 return cpumap_print_to_pagebuf(true, buf, cpumask_of(pmu->cpu)); 224} 225 226static struct device_attribute ddr_perf_cpumask_attr = 227 __ATTR(cpumask, 0444, ddr_perf_cpumask_show, NULL); 228 229static struct attribute *ddr_perf_cpumask_attrs[] = { 230 &ddr_perf_cpumask_attr.attr, 231 NULL, 232}; 233 234static const struct attribute_group ddr_perf_cpumask_attr_group = { 235 .attrs = ddr_perf_cpumask_attrs, 236}; 237 238static ssize_t 239ddr_pmu_event_show(struct device *dev, struct device_attribute *attr, 240 char *page) 241{ 242 struct perf_pmu_events_attr *pmu_attr; 243 244 pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr); 245 return sysfs_emit(page, "event=0x%02llx\n", pmu_attr->id); 246} 247 248#define IMX8_DDR_PMU_EVENT_ATTR(_name, _id) \ 249 PMU_EVENT_ATTR_ID(_name, ddr_pmu_event_show, _id) 250 251static struct attribute *ddr_perf_events_attrs[] = { 252 IMX8_DDR_PMU_EVENT_ATTR(cycles, EVENT_CYCLES_ID), 253 IMX8_DDR_PMU_EVENT_ATTR(selfresh, 0x01), 254 IMX8_DDR_PMU_EVENT_ATTR(read-accesses, 0x04), 255 IMX8_DDR_PMU_EVENT_ATTR(write-accesses, 0x05), 256 IMX8_DDR_PMU_EVENT_ATTR(read-queue-depth, 0x08), 257 IMX8_DDR_PMU_EVENT_ATTR(write-queue-depth, 0x09), 258 IMX8_DDR_PMU_EVENT_ATTR(lp-read-credit-cnt, 0x10), 259 IMX8_DDR_PMU_EVENT_ATTR(hp-read-credit-cnt, 0x11), 260 IMX8_DDR_PMU_EVENT_ATTR(write-credit-cnt, 0x12), 261 IMX8_DDR_PMU_EVENT_ATTR(read-command, 0x20), 262 IMX8_DDR_PMU_EVENT_ATTR(write-command, 0x21), 263 IMX8_DDR_PMU_EVENT_ATTR(read-modify-write-command, 0x22), 264 IMX8_DDR_PMU_EVENT_ATTR(hp-read, 0x23), 265 IMX8_DDR_PMU_EVENT_ATTR(hp-req-nocredit, 0x24), 266 IMX8_DDR_PMU_EVENT_ATTR(hp-xact-credit, 0x25), 267 IMX8_DDR_PMU_EVENT_ATTR(lp-req-nocredit, 0x26), 268 IMX8_DDR_PMU_EVENT_ATTR(lp-xact-credit, 0x27), 269 IMX8_DDR_PMU_EVENT_ATTR(wr-xact-credit, 0x29), 270 IMX8_DDR_PMU_EVENT_ATTR(read-cycles, 0x2a), 271 IMX8_DDR_PMU_EVENT_ATTR(write-cycles, 0x2b), 272 IMX8_DDR_PMU_EVENT_ATTR(read-write-transition, 0x30), 273 IMX8_DDR_PMU_EVENT_ATTR(precharge, 0x31), 274 IMX8_DDR_PMU_EVENT_ATTR(activate, 0x32), 275 IMX8_DDR_PMU_EVENT_ATTR(load-mode, 0x33), 276 IMX8_DDR_PMU_EVENT_ATTR(perf-mwr, 0x34), 277 IMX8_DDR_PMU_EVENT_ATTR(read, 0x35), 278 IMX8_DDR_PMU_EVENT_ATTR(read-activate, 0x36), 279 IMX8_DDR_PMU_EVENT_ATTR(refresh, 0x37), 280 IMX8_DDR_PMU_EVENT_ATTR(write, 0x38), 281 IMX8_DDR_PMU_EVENT_ATTR(raw-hazard, 0x39), 282 IMX8_DDR_PMU_EVENT_ATTR(axid-read, 0x41), 283 IMX8_DDR_PMU_EVENT_ATTR(axid-write, 0x42), 284 NULL, 285}; 286 287static const struct attribute_group ddr_perf_events_attr_group = { 288 .name = "events", 289 .attrs = ddr_perf_events_attrs, 290}; 291 292PMU_FORMAT_ATTR(event, "config:0-7"); 293PMU_FORMAT_ATTR(axi_id, "config1:0-15"); 294PMU_FORMAT_ATTR(axi_mask, "config1:16-31"); 295PMU_FORMAT_ATTR(axi_port, "config2:0-2"); 296PMU_FORMAT_ATTR(axi_channel, "config2:3-3"); 297 298static struct attribute *ddr_perf_format_attrs[] = { 299 &format_attr_event.attr, 300 &format_attr_axi_id.attr, 301 &format_attr_axi_mask.attr, 302 &format_attr_axi_port.attr, 303 &format_attr_axi_channel.attr, 304 NULL, 305}; 306 307static const struct attribute_group ddr_perf_format_attr_group = { 308 .name = "format", 309 .attrs = ddr_perf_format_attrs, 310}; 311 312static const struct attribute_group *attr_groups[] = { 313 &ddr_perf_events_attr_group, 314 &ddr_perf_format_attr_group, 315 &ddr_perf_cpumask_attr_group, 316 &ddr_perf_filter_cap_attr_group, 317 &ddr_perf_identifier_attr_group, 318 NULL, 319}; 320 321static bool ddr_perf_is_filtered(struct perf_event *event) 322{ 323 return event->attr.config == 0x41 || event->attr.config == 0x42; 324} 325 326static u32 ddr_perf_filter_val(struct perf_event *event) 327{ 328 return event->attr.config1; 329} 330 331static bool ddr_perf_filters_compatible(struct perf_event *a, 332 struct perf_event *b) 333{ 334 if (!ddr_perf_is_filtered(a)) 335 return true; 336 if (!ddr_perf_is_filtered(b)) 337 return true; 338 return ddr_perf_filter_val(a) == ddr_perf_filter_val(b); 339} 340 341static bool ddr_perf_is_enhanced_filtered(struct perf_event *event) 342{ 343 unsigned int filt; 344 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu); 345 346 filt = pmu->devtype_data->quirks & DDR_CAP_AXI_ID_FILTER_ENHANCED; 347 return (filt == DDR_CAP_AXI_ID_FILTER_ENHANCED) && 348 ddr_perf_is_filtered(event); 349} 350 351static u32 ddr_perf_alloc_counter(struct ddr_pmu *pmu, int event) 352{ 353 int i; 354 355 /* 356 * Always map cycle event to counter 0 357 * Cycles counter is dedicated for cycle event 358 * can't used for the other events 359 */ 360 if (event == EVENT_CYCLES_ID) { 361 if (pmu->events[EVENT_CYCLES_COUNTER] == NULL) 362 return EVENT_CYCLES_COUNTER; 363 else 364 return -ENOENT; 365 } 366 367 for (i = 1; i < NUM_COUNTERS; i++) { 368 if (pmu->events[i] == NULL) 369 return i; 370 } 371 372 return -ENOENT; 373} 374 375static void ddr_perf_free_counter(struct ddr_pmu *pmu, int counter) 376{ 377 pmu->events[counter] = NULL; 378} 379 380static u32 ddr_perf_read_counter(struct ddr_pmu *pmu, int counter) 381{ 382 struct perf_event *event = pmu->events[counter]; 383 void __iomem *base = pmu->base; 384 385 /* 386 * return bytes instead of bursts from ddr transaction for 387 * axid-read and axid-write event if PMU core supports enhanced 388 * filter. 389 */ 390 base += ddr_perf_is_enhanced_filtered(event) ? COUNTER_DPCR1 : 391 COUNTER_READ; 392 return readl_relaxed(base + counter * 4); 393} 394 395static int ddr_perf_event_init(struct perf_event *event) 396{ 397 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu); 398 struct hw_perf_event *hwc = &event->hw; 399 struct perf_event *sibling; 400 401 if (event->attr.type != event->pmu->type) 402 return -ENOENT; 403 404 if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK) 405 return -EOPNOTSUPP; 406 407 if (event->cpu < 0) { 408 dev_warn(pmu->dev, "Can't provide per-task data!\n"); 409 return -EOPNOTSUPP; 410 } 411 412 /* 413 * We must NOT create groups containing mixed PMUs, although software 414 * events are acceptable (for example to create a CCN group 415 * periodically read when a hrtimer aka cpu-clock leader triggers). 416 */ 417 if (event->group_leader->pmu != event->pmu && 418 !is_software_event(event->group_leader)) 419 return -EINVAL; 420 421 if (pmu->devtype_data->quirks & DDR_CAP_AXI_ID_FILTER) { 422 if (!ddr_perf_filters_compatible(event, event->group_leader)) 423 return -EINVAL; 424 for_each_sibling_event(sibling, event->group_leader) { 425 if (!ddr_perf_filters_compatible(event, sibling)) 426 return -EINVAL; 427 } 428 } 429 430 for_each_sibling_event(sibling, event->group_leader) { 431 if (sibling->pmu != event->pmu && 432 !is_software_event(sibling)) 433 return -EINVAL; 434 } 435 436 event->cpu = pmu->cpu; 437 hwc->idx = -1; 438 439 return 0; 440} 441 442static void ddr_perf_counter_enable(struct ddr_pmu *pmu, int config, 443 int counter, bool enable) 444{ 445 u8 reg = counter * 4 + COUNTER_CNTL; 446 int val; 447 448 if (enable) { 449 /* 450 * cycle counter is special which should firstly write 0 then 451 * write 1 into CLEAR bit to clear it. Other counters only 452 * need write 0 into CLEAR bit and it turns out to be 1 by 453 * hardware. Below enable flow is harmless for all counters. 454 */ 455 writel(0, pmu->base + reg); 456 val = CNTL_EN | CNTL_CLEAR; 457 val |= FIELD_PREP(CNTL_CSV_MASK, config); 458 459 /* 460 * On i.MX8MP we need to bias the cycle counter to overflow more often. 461 * We do this by initializing bits [23:16] of the counter value via the 462 * COUNTER_CTRL Counter Parameter (CP) field. 463 */ 464 if (pmu->devtype_data->quirks & DDR_CAP_AXI_ID_FILTER_ENHANCED) { 465 if (counter == EVENT_CYCLES_COUNTER) 466 val |= FIELD_PREP(CNTL_CP_MASK, 0xf0); 467 } 468 469 writel(val, pmu->base + reg); 470 } else { 471 /* Disable counter */ 472 val = readl_relaxed(pmu->base + reg) & CNTL_EN_MASK; 473 writel(val, pmu->base + reg); 474 } 475} 476 477static bool ddr_perf_counter_overflow(struct ddr_pmu *pmu, int counter) 478{ 479 int val; 480 481 val = readl_relaxed(pmu->base + counter * 4 + COUNTER_CNTL); 482 483 return val & CNTL_OVER; 484} 485 486static void ddr_perf_counter_clear(struct ddr_pmu *pmu, int counter) 487{ 488 u8 reg = counter * 4 + COUNTER_CNTL; 489 int val; 490 491 val = readl_relaxed(pmu->base + reg); 492 val &= ~CNTL_CLEAR; 493 writel(val, pmu->base + reg); 494 495 val |= CNTL_CLEAR; 496 writel(val, pmu->base + reg); 497} 498 499static void ddr_perf_event_update(struct perf_event *event) 500{ 501 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu); 502 struct hw_perf_event *hwc = &event->hw; 503 u64 new_raw_count; 504 int counter = hwc->idx; 505 int ret; 506 507 new_raw_count = ddr_perf_read_counter(pmu, counter); 508 /* Remove the bias applied in ddr_perf_counter_enable(). */ 509 if (pmu->devtype_data->quirks & DDR_CAP_AXI_ID_FILTER_ENHANCED) { 510 if (counter == EVENT_CYCLES_COUNTER) 511 new_raw_count &= CYCLES_COUNTER_MASK; 512 } 513 514 local64_add(new_raw_count, &event->count); 515 516 /* 517 * For legacy SoCs: event counter continue counting when overflow, 518 * no need to clear the counter. 519 * For new SoCs: event counter stop counting when overflow, need 520 * clear counter to let it count again. 521 */ 522 if (counter != EVENT_CYCLES_COUNTER) { 523 ret = ddr_perf_counter_overflow(pmu, counter); 524 if (ret) 525 dev_warn_ratelimited(pmu->dev, "events lost due to counter overflow (config 0x%llx)\n", 526 event->attr.config); 527 } 528 529 /* clear counter every time for both cycle counter and event counter */ 530 ddr_perf_counter_clear(pmu, counter); 531} 532 533static void ddr_perf_event_start(struct perf_event *event, int flags) 534{ 535 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu); 536 struct hw_perf_event *hwc = &event->hw; 537 int counter = hwc->idx; 538 539 local64_set(&hwc->prev_count, 0); 540 541 ddr_perf_counter_enable(pmu, event->attr.config, counter, true); 542 543 if (!pmu->active_counter++) 544 ddr_perf_counter_enable(pmu, EVENT_CYCLES_ID, 545 EVENT_CYCLES_COUNTER, true); 546 547 hwc->state = 0; 548} 549 550static int ddr_perf_event_add(struct perf_event *event, int flags) 551{ 552 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu); 553 struct hw_perf_event *hwc = &event->hw; 554 int counter; 555 int cfg = event->attr.config; 556 int cfg1 = event->attr.config1; 557 int cfg2 = event->attr.config2; 558 559 if (pmu->devtype_data->quirks & DDR_CAP_AXI_ID_FILTER) { 560 int i; 561 562 for (i = 1; i < NUM_COUNTERS; i++) { 563 if (pmu->events[i] && 564 !ddr_perf_filters_compatible(event, pmu->events[i])) 565 return -EINVAL; 566 } 567 568 if (ddr_perf_is_filtered(event)) { 569 /* revert axi id masking(axi_mask) value */ 570 cfg1 ^= AXI_MASKING_REVERT; 571 writel(cfg1, pmu->base + COUNTER_DPCR1); 572 } 573 } 574 575 counter = ddr_perf_alloc_counter(pmu, cfg); 576 if (counter < 0) { 577 dev_dbg(pmu->dev, "There are not enough counters\n"); 578 return -EOPNOTSUPP; 579 } 580 581 if (pmu->devtype_data->quirks & DDR_CAP_AXI_ID_PORT_CHANNEL_FILTER) { 582 if (ddr_perf_is_filtered(event)) { 583 /* revert axi id masking(axi_mask) value */ 584 cfg1 ^= AXI_MASKING_REVERT; 585 writel(cfg1, pmu->base + COUNTER_MASK_COMP + ((counter - 1) << 4)); 586 587 if (cfg == 0x41) { 588 /* revert axi read channel(axi_channel) value */ 589 cfg2 ^= READ_CHANNEL_REVERT; 590 cfg2 |= FIELD_PREP(READ_PORT_MASK, cfg2); 591 } else { 592 /* revert axi write channel(axi_channel) value */ 593 cfg2 ^= WRITE_CHANNEL_REVERT; 594 cfg2 |= FIELD_PREP(WRITE_PORT_MASK, cfg2); 595 } 596 597 writel(cfg2, pmu->base + COUNTER_MUX_CNTL + ((counter - 1) << 4)); 598 } 599 } 600 601 pmu->events[counter] = event; 602 hwc->idx = counter; 603 604 hwc->state |= PERF_HES_STOPPED; 605 606 if (flags & PERF_EF_START) 607 ddr_perf_event_start(event, flags); 608 609 return 0; 610} 611 612static void ddr_perf_event_stop(struct perf_event *event, int flags) 613{ 614 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu); 615 struct hw_perf_event *hwc = &event->hw; 616 int counter = hwc->idx; 617 618 ddr_perf_counter_enable(pmu, event->attr.config, counter, false); 619 ddr_perf_event_update(event); 620 621 if (!--pmu->active_counter) 622 ddr_perf_counter_enable(pmu, EVENT_CYCLES_ID, 623 EVENT_CYCLES_COUNTER, false); 624 625 hwc->state |= PERF_HES_STOPPED; 626} 627 628static void ddr_perf_event_del(struct perf_event *event, int flags) 629{ 630 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu); 631 struct hw_perf_event *hwc = &event->hw; 632 int counter = hwc->idx; 633 634 ddr_perf_event_stop(event, PERF_EF_UPDATE); 635 636 ddr_perf_free_counter(pmu, counter); 637 hwc->idx = -1; 638} 639 640static void ddr_perf_pmu_enable(struct pmu *pmu) 641{ 642} 643 644static void ddr_perf_pmu_disable(struct pmu *pmu) 645{ 646} 647 648static int ddr_perf_init(struct ddr_pmu *pmu, void __iomem *base, 649 struct device *dev) 650{ 651 *pmu = (struct ddr_pmu) { 652 .pmu = (struct pmu) { 653 .module = THIS_MODULE, 654 .capabilities = PERF_PMU_CAP_NO_EXCLUDE, 655 .task_ctx_nr = perf_invalid_context, 656 .attr_groups = attr_groups, 657 .event_init = ddr_perf_event_init, 658 .add = ddr_perf_event_add, 659 .del = ddr_perf_event_del, 660 .start = ddr_perf_event_start, 661 .stop = ddr_perf_event_stop, 662 .read = ddr_perf_event_update, 663 .pmu_enable = ddr_perf_pmu_enable, 664 .pmu_disable = ddr_perf_pmu_disable, 665 }, 666 .base = base, 667 .dev = dev, 668 }; 669 670 pmu->id = ida_alloc(&ddr_ida, GFP_KERNEL); 671 return pmu->id; 672} 673 674static irqreturn_t ddr_perf_irq_handler(int irq, void *p) 675{ 676 int i; 677 struct ddr_pmu *pmu = (struct ddr_pmu *) p; 678 struct perf_event *event; 679 680 /* all counter will stop if cycle counter disabled */ 681 ddr_perf_counter_enable(pmu, 682 EVENT_CYCLES_ID, 683 EVENT_CYCLES_COUNTER, 684 false); 685 /* 686 * When the cycle counter overflows, all counters are stopped, 687 * and an IRQ is raised. If any other counter overflows, it 688 * continues counting, and no IRQ is raised. But for new SoCs, 689 * such as i.MX8MP, event counter would stop when overflow, so 690 * we need use cycle counter to stop overflow of event counter. 691 * 692 * Cycles occur at least 4 times as often as other events, so we 693 * can update all events on a cycle counter overflow and not 694 * lose events. 695 * 696 */ 697 for (i = 0; i < NUM_COUNTERS; i++) { 698 699 if (!pmu->events[i]) 700 continue; 701 702 event = pmu->events[i]; 703 704 ddr_perf_event_update(event); 705 } 706 707 ddr_perf_counter_enable(pmu, 708 EVENT_CYCLES_ID, 709 EVENT_CYCLES_COUNTER, 710 true); 711 712 return IRQ_HANDLED; 713} 714 715static int ddr_perf_offline_cpu(unsigned int cpu, struct hlist_node *node) 716{ 717 struct ddr_pmu *pmu = hlist_entry_safe(node, struct ddr_pmu, node); 718 int target; 719 720 if (cpu != pmu->cpu) 721 return 0; 722 723 target = cpumask_any_but(cpu_online_mask, cpu); 724 if (target >= nr_cpu_ids) 725 return 0; 726 727 perf_pmu_migrate_context(&pmu->pmu, cpu, target); 728 pmu->cpu = target; 729 730 WARN_ON(irq_set_affinity(pmu->irq, cpumask_of(pmu->cpu))); 731 732 return 0; 733} 734 735static int ddr_perf_probe(struct platform_device *pdev) 736{ 737 struct ddr_pmu *pmu; 738 struct device_node *np; 739 void __iomem *base; 740 char *name; 741 int num; 742 int ret; 743 int irq; 744 745 base = devm_platform_ioremap_resource(pdev, 0); 746 if (IS_ERR(base)) 747 return PTR_ERR(base); 748 749 np = pdev->dev.of_node; 750 751 pmu = devm_kzalloc(&pdev->dev, sizeof(*pmu), GFP_KERNEL); 752 if (!pmu) 753 return -ENOMEM; 754 755 num = ddr_perf_init(pmu, base, &pdev->dev); 756 757 platform_set_drvdata(pdev, pmu); 758 759 name = devm_kasprintf(&pdev->dev, GFP_KERNEL, DDR_PERF_DEV_NAME "%d", 760 num); 761 if (!name) { 762 ret = -ENOMEM; 763 goto cpuhp_state_err; 764 } 765 766 pmu->devtype_data = of_device_get_match_data(&pdev->dev); 767 768 pmu->cpu = raw_smp_processor_id(); 769 ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, 770 DDR_CPUHP_CB_NAME, 771 NULL, 772 ddr_perf_offline_cpu); 773 774 if (ret < 0) { 775 dev_err(&pdev->dev, "cpuhp_setup_state_multi failed\n"); 776 goto cpuhp_state_err; 777 } 778 779 pmu->cpuhp_state = ret; 780 781 /* Register the pmu instance for cpu hotplug */ 782 ret = cpuhp_state_add_instance_nocalls(pmu->cpuhp_state, &pmu->node); 783 if (ret) { 784 dev_err(&pdev->dev, "Error %d registering hotplug\n", ret); 785 goto cpuhp_instance_err; 786 } 787 788 /* Request irq */ 789 irq = of_irq_get(np, 0); 790 if (irq < 0) { 791 dev_err(&pdev->dev, "Failed to get irq: %d", irq); 792 ret = irq; 793 goto ddr_perf_err; 794 } 795 796 ret = devm_request_irq(&pdev->dev, irq, 797 ddr_perf_irq_handler, 798 IRQF_NOBALANCING | IRQF_NO_THREAD, 799 DDR_CPUHP_CB_NAME, 800 pmu); 801 if (ret < 0) { 802 dev_err(&pdev->dev, "Request irq failed: %d", ret); 803 goto ddr_perf_err; 804 } 805 806 pmu->irq = irq; 807 ret = irq_set_affinity(pmu->irq, cpumask_of(pmu->cpu)); 808 if (ret) { 809 dev_err(pmu->dev, "Failed to set interrupt affinity!\n"); 810 goto ddr_perf_err; 811 } 812 813 ret = perf_pmu_register(&pmu->pmu, name, -1); 814 if (ret) 815 goto ddr_perf_err; 816 817 return 0; 818 819ddr_perf_err: 820 cpuhp_state_remove_instance_nocalls(pmu->cpuhp_state, &pmu->node); 821cpuhp_instance_err: 822 cpuhp_remove_multi_state(pmu->cpuhp_state); 823cpuhp_state_err: 824 ida_free(&ddr_ida, pmu->id); 825 dev_warn(&pdev->dev, "i.MX8 DDR Perf PMU failed (%d), disabled\n", ret); 826 return ret; 827} 828 829static void ddr_perf_remove(struct platform_device *pdev) 830{ 831 struct ddr_pmu *pmu = platform_get_drvdata(pdev); 832 833 cpuhp_state_remove_instance_nocalls(pmu->cpuhp_state, &pmu->node); 834 cpuhp_remove_multi_state(pmu->cpuhp_state); 835 836 perf_pmu_unregister(&pmu->pmu); 837 838 ida_free(&ddr_ida, pmu->id); 839} 840 841static struct platform_driver imx_ddr_pmu_driver = { 842 .driver = { 843 .name = "imx-ddr-pmu", 844 .of_match_table = imx_ddr_pmu_dt_ids, 845 .suppress_bind_attrs = true, 846 }, 847 .probe = ddr_perf_probe, 848 .remove_new = ddr_perf_remove, 849}; 850 851module_platform_driver(imx_ddr_pmu_driver); 852MODULE_LICENSE("GPL v2"); 853