Searched refs:uvd (Results 1 - 22 of 22) sorted by relevance

/linux-master/drivers/gpu/drm/radeon/
H A Duvd_v4_2.c46 if (rdev->uvd.fw_header_present)
47 addr = (rdev->uvd.gpu_addr + 0x200) >> 3;
49 addr = rdev->uvd.gpu_addr >> 3;
62 (RADEON_UVD_SESSION_SIZE * rdev->uvd.max_handles)) >> 3;
67 addr = (rdev->uvd.gpu_addr >> 28) & 0xF;
71 addr = (rdev->uvd.gpu_addr >> 32) & 0xFF;
74 if (rdev->uvd.fw_header_present)
75 WREG32(UVD_GP_SCRATCH4, rdev->uvd.max_handles);
H A Dradeon_uvd.c72 INIT_DELAYED_WORK(&rdev->uvd.idle_work, radeon_uvd_idle_work_handler);
137 rdev->uvd.fw_header_present = false;
138 rdev->uvd.max_handles = RADEON_DEFAULT_UVD_HANDLES;
153 rdev->uvd.fw_header_present = true;
168 rdev->uvd.max_handles = RADEON_MAX_UVD_HANDLES;
188 RADEON_UVD_SESSION_SIZE * rdev->uvd.max_handles;
191 NULL, &rdev->uvd.vcpu_bo);
197 r = radeon_bo_reserve(rdev->uvd.vcpu_bo, false);
199 radeon_bo_unref(&rdev->uvd.vcpu_bo);
204 r = radeon_bo_pin(rdev->uvd
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H A Duvd_v2_2.c113 addr = rdev->uvd.gpu_addr >> 3;
125 (RADEON_UVD_SESSION_SIZE * rdev->uvd.max_handles)) >> 3;
130 addr = (rdev->uvd.gpu_addr >> 28) & 0xF;
134 addr = (rdev->uvd.gpu_addr >> 32) & 0xFF;
H A Duvd_v1_0.c121 addr = (rdev->uvd.gpu_addr >> 3) + 16;
133 (RADEON_UVD_SESSION_SIZE * rdev->uvd.max_handles)) >> 3;
138 addr = (rdev->uvd.gpu_addr >> 28) & 0xF;
142 addr = (rdev->uvd.gpu_addr >> 32) & 0xFF;
145 WREG32(UVD_FW_START, *((uint32_t *)rdev->uvd.cpu_addr));
H A Dradeon_drv.c236 MODULE_PARM_DESC(uvd, "uvd enable/disable uvd support (1 = enable, 0 = disable)");
237 module_param_named(uvd, radeon_uvd, int, 0444);
H A Dradeon_fence.c824 rdev->fence_drv[ring].cpu_addr = rdev->uvd.cpu_addr + index;
825 rdev->fence_drv[ring].gpu_addr = rdev->uvd.gpu_addr + index;
1023 case R600_RING_TYPE_UVD_INDEX: return "radeon.uvd";
H A Dradeon.h1540 /* default uvd power state */
2378 struct radeon_uvd uvd; member in struct:radeon_device
/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_uvd.c42 #include "uvd/uvd_4_2_d.h"
155 if (adev->uvd.address_64_bit)
192 INIT_DELAYED_WORK(&adev->uvd.idle_work, amdgpu_uvd_idle_work_handler);
263 r = amdgpu_ucode_request(adev, &adev->uvd.fw, fw_name);
267 amdgpu_ucode_release(&adev->uvd.fw);
272 adev->uvd.max_handles = AMDGPU_DEFAULT_UVD_HANDLES;
274 hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
293 adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES;
295 adev->uvd.fw_version = ((version_major << 24) | (version_minor << 16) |
300 (adev->uvd
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H A Duvd_v7_0.c34 #include "uvd/uvd_7_0_offset.h"
35 #include "uvd/uvd_7_0_sh_mask.h"
42 #include "ivsrcid/uvd/irqsrcs_uvd_7_0.h"
89 if (ring == &adev->uvd.inst[ring->me].ring_enc[0])
123 if (ring == &adev->uvd.inst[ring->me].ring_enc[0])
161 if (ring == &adev->uvd.inst[ring->me].ring_enc[0])
342 struct amdgpu_bo *bo = ring->adev->uvd.ib_bo;
372 adev->uvd.num_uvd_inst = UVD7_MAX_HW_INSTANCES_VEGA20;
373 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
376 adev->uvd
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H A Duvd_v6_0.c30 #include "uvd/uvd_6_0_d.h"
31 #include "uvd/uvd_6_0_sh_mask.h"
67 (!adev->uvd.fw_version || adev->uvd.fw_version >= FW_1_130_16));
95 if (ring == &adev->uvd.inst->ring_enc[0])
125 if (ring == &adev->uvd.inst->ring_enc[0])
156 if (ring == &adev->uvd.inst->ring_enc[0])
335 struct amdgpu_bo *bo = ring->adev->uvd.ib_bo;
360 adev->uvd.num_uvd_inst = 1;
369 adev->uvd
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H A Duvd_v3_1.c31 #include "uvd/uvd_3_1_d.h"
32 #include "uvd/uvd_3_1_sh_mask.h"
203 adev->uvd.inst->ring.funcs = &uvd_v3_1_ring_funcs;
246 addr = (adev->uvd.inst->gpu_addr + AMDGPU_UVD_FIRMWARE_OFFSET) >> 3;
258 (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles)) >> 3;
263 addr = (adev->uvd.inst->gpu_addr >> 28) & 0xF;
267 addr = (adev->uvd.inst->gpu_addr >> 32) & 0xFF;
285 uint32_t keysel = adev->uvd.keyselect;
322 struct amdgpu_ring *ring = &adev->uvd.inst->ring;
330 /* set uvd bus
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H A Duvd_v4_2.c31 #include "uvd/uvd_4_2_d.h"
32 #include "uvd/uvd_4_2_sh_mask.h"
96 adev->uvd.num_uvd_inst = 1;
111 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 124, &adev->uvd.inst->irq);
119 ring = &adev->uvd.inst->ring;
120 sprintf(ring->name, "uvd");
121 r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst->irq, 0,
157 struct amdgpu_ring *ring = &adev->uvd.inst->ring;
213 cancel_delayed_work_sync(&adev->uvd.idle_work);
244 cancel_delayed_work_sync(&adev->uvd
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H A Duvd_v5_0.c31 #include "uvd/uvd_5_0_d.h"
32 #include "uvd/uvd_5_0_sh_mask.h"
94 adev->uvd.num_uvd_inst = 1;
109 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_UVD_SYSTEM_MESSAGE, &adev->uvd.inst->irq);
117 ring = &adev->uvd.inst->ring;
118 sprintf(ring->name, "uvd");
119 r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst->irq, 0,
153 struct amdgpu_ring *ring = &adev->uvd.inst->ring;
211 cancel_delayed_work_sync(&adev->uvd.idle_work);
242 cancel_delayed_work_sync(&adev->uvd
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H A Damdgpu_uvd.h37 (AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(((const struct common_firmware_header *)(adev)->uvd.fw->data)->ucode_size_bytes) + \
H A Damdgpu_kms.c251 fw_info->ver = adev->uvd.fw_version;
443 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
444 if (adev->uvd.harvest_config & (1 << i))
447 if (adev->uvd.inst[i].ring.sched.ready)
463 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
464 if (adev->uvd.harvest_config & (1 << i))
467 for (j = 0; j < adev->uvd.num_enc_rings; j++)
468 if (adev->uvd.inst[i].ring_enc[j].sched.ready)
694 count = adev->uvd.num_uvd_inst;
1050 handle.uvd_max_handles = adev->uvd
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H A Damdgpu_fence.c484 index = ALIGN(adev->uvd.fw->size, 8);
485 ring->fence_drv.cpu_addr = adev->uvd.inst[ring->me].cpu_addr + index;
486 ring->fence_drv.gpu_addr = adev->uvd.inst[ring->me].gpu_addr + index;
H A Damdgpu_virt.c508 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_UVD, adev->uvd.fw_version);
H A Damdgpu_ucode.c713 FW_VERSION_ATTR(uvd_fw_version, 0444, uvd.fw_version);
H A Damdgpu.h997 /* uvd */
998 struct amdgpu_uvd uvd; member in struct:amdgpu_device
/linux-master/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dsmu8_hwmgr.h135 uint32_t uvd : 1; member in struct:pp_disable_nb_ps_flags::__anon693::__anon694
H A Dsmu10_hwmgr.h112 uint32_t uvd : 1; member in struct:pp_disable_nbpslo_flags::__anon485::__anon486
H A Dsmu8_hwmgr.c509 /* uvd breakdown */
1996 adev->uvd.decode_image_width >= WIDTH_4K)

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