| /linux-master/drivers/gpu/drm/amd/display/dc/hwss/dce/ |
| H A D | dce_hwseq.c | 177 unsigned int tg_inst)
180 REG_UPDATE(PIXEL_RATE_CNTL[tg_inst],
186 REG_UPDATE_2(PHYPLL_PIXEL_RATE_CNTL[tg_inst],
190 REG_UPDATE(PIXEL_RATE_CNTL[tg_inst],
196 REG_UPDATE_2(PIXEL_RATE_CNTL[tg_inst],
200 if (REG(PHYPLL_PIXEL_RATE_CNTL[tg_inst]))
201 REG_UPDATE(PHYPLL_PIXEL_RATE_CNTL[tg_inst],
205 clk_src->id, tg_inst);
175 dce_crtc_switch_to_clk_src(struct dce_hwseq *hws, struct clock_source *clk_src, unsigned int tg_inst) argument
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| H A D | dce_hwseq.h | 1267 unsigned int tg_inst);
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| /linux-master/drivers/gpu/drm/amd/display/dc/virtual/ |
| H A D | virtual_stream_encoder.c | 93 int tg_inst)
98 int tg_inst,
91 virtual_dig_connect_to_otg( struct stream_encoder *enc, int tg_inst) argument
96 virtual_setup_stereo_sync( struct stream_encoder *enc, int tg_inst, bool enable) argument
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| /linux-master/drivers/gpu/drm/amd/display/dc/ |
| H A D | dc_dmub_srv.h | 82 void dc_dmub_srv_drr_update_cmd(struct dc *dc, uint32_t tg_inst, uint32_t vtotal_min, uint32_t vtotal_max);
84 void dc_dmub_srv_set_drr_manual_trigger_cmd(struct dc *dc, uint32_t tg_inst);
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| H A D | dc_dmub_srv.c | 353 void dc_dmub_srv_drr_update_cmd(struct dc *dc, uint32_t tg_inst, uint32_t vtotal_min, uint32_t vtotal_max) argument
361 cmd.drr_update.dmub_optc_state_req.tg_inst = tg_inst;
369 void dc_dmub_srv_set_drr_manual_trigger_cmd(struct dc *dc, uint32_t tg_inst) argument
375 cmd.drr_update.dmub_optc_state_req.tg_inst = tg_inst;
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| /linux-master/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| H A D | stream_encoder.h | 219 int tg_inst,
227 int tg_inst);
|
| /linux-master/drivers/gpu/drm/amd/display/dc/dce/ |
| H A D | dce_stream_encoder.c | 1488 int tg_inst, bool enable)
1491 REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, tg_inst);
1497 int tg_inst)
1501 REG_UPDATE(DIG_FE_CNTL, DIG_SOURCE_SELECT, tg_inst);
1507 uint32_t tg_inst = 0; local
1510 REG_GET(DIG_FE_CNTL, DIG_SOURCE_SELECT, &tg_inst);
1512 return tg_inst;
1486 setup_stereo_sync( struct stream_encoder *enc, int tg_inst, bool enable) argument
1495 dig_connect_to_otg( struct stream_encoder *enc, int tg_inst) argument
|
| /linux-master/drivers/gpu/drm/amd/display/dc/dcn10/ |
| H A D | dcn10_stream_encoder.c | 1483 int tg_inst, bool enable)
1486 REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, tg_inst);
1492 int tg_inst)
1496 REG_UPDATE(DIG_FE_CNTL, DIG_SOURCE_SELECT, tg_inst);
1502 uint32_t tg_inst = 0; local
1505 REG_GET(DIG_FE_CNTL, DIG_SOURCE_SELECT, &tg_inst);
1507 return tg_inst;
1481 enc1_setup_stereo_sync( struct stream_encoder *enc, int tg_inst, bool enable) argument
1490 enc1_dig_connect_to_otg( struct stream_encoder *enc, int tg_inst) argument
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| H A D | dcn10_stream_encoder.h | 684 int tg_inst, bool enable);
716 int tg_inst);
|
| /linux-master/drivers/gpu/drm/amd/display/dc/core/ |
| H A D | dc_resource.c | 3216 unsigned int i, inst, tg_inst = 0; local
3231 tg_inst = pool->stream_enc[i]->funcs->dig_source_otg(
3237 // tg_inst not found
3241 if (tg_inst >= pool->timing_generator_count)
3244 if (!res_ctx->pipe_ctx[tg_inst].stream) {
3245 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[tg_inst];
3247 pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst];
3248 id_src[0] = tg_inst;
3255 id_src[0] = tg_inst;
3266 pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst];
3396 int tg_inst = pool->timing_generator_count - 1; local
[all...] |
| H A D | dc.c | 1274 unsigned int enc_inst, tg_inst = 0; local
1281 tg_inst = dc->res_pool->stream_enc[j]->funcs->dig_source_otg(
1289 tg_inst, &pix_clk_100hz);
1673 unsigned int i, enc_inst, tg_inst = 0; local
1697 tg_inst = dc->res_pool->stream_enc[i]->funcs->dig_source_otg(
1703 // tg_inst not found
1707 if (tg_inst >= dc->res_pool->timing_generator_count)
1710 if (tg_inst != link->link_enc->preferred_engine)
1713 tg = dc->res_pool->timing_generators[tg_inst];
1768 tg_inst,
[all...] |
| /linux-master/drivers/gpu/drm/amd/display/dmub/inc/ |
| H A D | dmub_cmd.h | 4070 uint32_t tg_inst; member in struct:dmub_optc_state
|