/linux-master/arch/powerpc/mm/book3s64/ |
H A D | slice.c | 34 static void slice_print_mask(const char *label, const struct slice_mask *mask) 48 static void slice_print_mask(const char *label, const struct slice_mask *mask) {} 61 struct slice_mask *ret) 117 static void slice_mask_for_free(struct mm_struct *mm, struct slice_mask *ret, 139 const struct slice_mask *available, 188 const struct slice_mask *mask, int psize) 193 struct slice_mask *psize_mask, *old_mask; 215 /* Update the slice_mask */ 234 /* Update the slice_mask */ 262 const struct slice_mask *availabl [all...] |
/linux-master/drivers/gpu/drm/i915/gt/ |
H A D | intel_sseu_debugfs.c | 36 sseu->slice_mask = BIT(0); 87 sseu->slice_mask |= BIT(s); 140 sseu->slice_mask |= BIT(s); 175 sseu->slice_mask = slice_info & GEN8_LSLICESTAT_MASK; 177 if (sseu->slice_mask) { 179 for (s = 0; s < fls(sseu->slice_mask); s++) 185 for (s = 0; s < fls(sseu->slice_mask); s++) { 201 sseu->slice_mask); 203 hweight8(sseu->slice_mask));
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H A D | intel_sseu.h | 69 u8 slice_mask; member in struct:sseu_dev_info 102 u8 slice_mask; member in struct:intel_sseu 112 .slice_mask = sseu->slice_mask,
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H A D | intel_sseu.c | 156 sseu->slice_mask |= BIT(0); 172 sseu->slice_mask |= BIT(0); 338 sseu->slice_mask = BIT(0); 393 sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT; 412 if (!(sseu->slice_mask & BIT(s))) 467 !IS_GEN9_LP(i915) && hweight8(sseu->slice_mask) > 1; 498 sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT; 524 if (!(sseu->slice_mask & BIT(s))) 569 sseu->has_slice_pg = hweight8(sseu->slice_mask) > 1; 591 sseu->slice_mask 884 unsigned long slice_mask = 0; local [all...] |
H A D | intel_workarounds.c | 1122 slice = ffs(sseu->slice_mask) - 1; 1271 GEM_BUG_ON(hweight8(sseu->slice_mask) > 1); 1299 unsigned long slice, subslice = 0, slice_mask = 0; local 1330 slice_mask = intel_slicemask_from_xehp_dssmask(sseu->subslice_mask, 1344 if (slice_mask & lncf_mask) { 1345 slice_mask &= lncf_mask; 1350 if (slice_mask & gt->info.mslice_mask) { 1351 slice_mask &= gt->info.mslice_mask; 1355 if (IS_XEHPSDV(gt->i915) && slice_mask & BIT(0)) 1358 slice = __ffs(slice_mask); [all...] |
/linux-master/drivers/crypto/intel/qat/qat_common/ |
H A D | icp_qat_fw_loader_handle.h | 19 unsigned int slice_mask; member in struct:icp_qat_fw_loader_hal_handle
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H A D | qat_hal.c | 798 handle->hal_handle->slice_mask = hw_data->accel_mask;
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/linux-master/arch/powerpc/include/asm/book3s/64/ |
H A D | mmu-hash.h | 708 struct slice_mask { struct 721 struct slice_mask mask_64k; 723 struct slice_mask mask_4k; 725 struct slice_mask mask_16m; 726 struct slice_mask mask_16g;
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H A D | mmu.h | 169 static inline struct slice_mask *slice_mask_for_size(mm_context_t *ctx, int psize)
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/linux-master/drivers/gpu/drm/i915/ |
H A D | i915_getparam.c | 166 value = sseu->slice_mask;
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H A D | i915_query.c | 42 BUILD_BUG_ON(sizeof(u8) != sizeof(sseu->slice_mask)); 47 slice_length = sizeof(sseu->slice_mask); 73 &sseu->slice_mask, slice_length))
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H A D | i915_perf.c | 3202 out_sseu->slice_mask = 0x1;
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/linux-master/drivers/gpu/drm/i915/display/ |
H A D | intel_display_device.c | 450 .dbuf.slice_mask = BIT(DBUF_S1), 474 .dbuf.slice_mask = BIT(DBUF_S1), \ 514 .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \ 567 .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \ 655 .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | \ 722 .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | \
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H A D | intel_display_device.h | 140 u8 slice_mask; member in struct:intel_display_device_info::__anon14
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H A D | skl_watermark.c | 525 hweight8(DISPLAY_INFO(i915)->dbuf.slice_mask); 529 skl_ddb_entry_for_slices(struct drm_i915_private *i915, u8 slice_mask, argument 534 if (!slice_mask) { 540 ddb->start = (ffs(slice_mask) - 1) * slice_size; 541 ddb->end = fls(slice_mask) * slice_size; 547 static unsigned int mbus_ddb_offset(struct drm_i915_private *i915, u8 slice_mask) argument 551 if (slice_mask & (BIT(DBUF_S1) | BIT(DBUF_S2))) 552 slice_mask = BIT(DBUF_S1); 553 else if (slice_mask & (BIT(DBUF_S3) | BIT(DBUF_S4))) 554 slice_mask 566 u8 slice_mask = 0; local [all...] |
H A D | intel_display_power.c | 1079 u8 slice_mask = DISPLAY_INFO(dev_priv)->dbuf.slice_mask; local 1082 drm_WARN(&dev_priv->drm, req_slices & ~slice_mask, 1084 req_slices, slice_mask);
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H A D | intel_display.h | 115 for_each_if(DISPLAY_INFO(__dev_priv)->dbuf.slice_mask & BIT(__slice))
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/linux-master/drivers/gpu/drm/i915/gem/ |
H A D | i915_gem_context.c | 992 if (sseu.slice_mask && !WARN_ON(ce->engine->class != RENDER_CLASS)) 1903 if (!user->slice_mask || !user->subslice_mask || 1915 if (overflows_type(user->slice_mask, context->slice_mask) || 1924 if (user->slice_mask & ~device->slice_mask) 1933 context->slice_mask = user->slice_mask; 1940 unsigned int hw_s = hweight8(device->slice_mask); 1942 unsigned int req_s = hweight8(context->slice_mask); [all...] |
/linux-master/drivers/gpu/drm/i915/gem/selftests/ |
H A D | i915_gem_context.c | 1169 unsigned int slices = hweight32(ce->engine->sseu.slice_mask); 1226 hweight32(sseu.slice_mask), spin); 1271 if (hweight32(engine->sseu.slice_mask) < 2) 1282 pg_sseu.slice_mask = 1; 1288 hweight32(engine->sseu.slice_mask), 1289 hweight32(pg_sseu.slice_mask));
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/linux-master/drivers/gpu/drm/i915/gt/uc/ |
H A D | intel_guc_ads.c | 814 hweight8(gt->info.sseu.slice_mask));
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/linux-master/include/uapi/drm/ |
H A D | i915_drm.h | 2194 __u64 slice_mask; member in struct:drm_i915_gem_context_param_sseu
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/linux-master/tools/include/uapi/drm/ |
H A D | i915_drm.h | 2194 __u64 slice_mask; member in struct:drm_i915_gem_context_param_sseu
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