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Searched refs:rs1 (Results 1 - 15 of 15) sorted by relevance

/linux-master/arch/riscv/net/
H A D	bpf_jit.h	234 static inline u32 rv_r_insn(u8 funct7, u8 rs2, u8 rs1, u8 funct3, u8 rd, argument 237 return (funct7 << 25) \| (rs2 << 20) \| (rs1 << 15) \| (funct3 << 12) \| 241 static inline u32 rv_i_insn(u16 imm11_0, u8 rs1, u8 funct3, u8 rd, u8 opcode) argument 243 return (imm11_0 << 20) \| (rs1 << 15) \| (funct3 << 12) \| (rd << 7) \| 247 static inline u32 rv_s_insn(u16 imm11_0, u8 rs2, u8 rs1, u8 funct3, u8 opcode) argument 251 return (imm11_5 << 25) \| (rs2 << 20) \| (rs1 << 15) \| (funct3 << 12) \| 255 static inline u32 rv_b_insn(u16 imm12_1, u8 rs2, u8 rs1, u8 funct3, u8 opcode) argument 260 return (imm12 << 25) \| (rs2 << 20) \| (rs1 << 15) \| (funct3 << 12) \| 279 static inline u32 rv_amo_insn(u8 funct5, u8 aq, u8 rl, u8 rs2, u8 rs1, argument 284 return rv_r_insn(funct7, rs2, rs1, funct 312 rv_cl_insn(u8 funct3, u32 imm_hi, u8 rs1, u32 imm_lo, u8 rd, u8 op) argument 319 rv_cs_insn(u8 funct3, u32 imm_hi, u8 rs1, u32 imm_lo, u8 rs2, u8 op) argument 342 rv_addi(u8 rd, u8 rs1, u16 imm11_0) argument 347 rv_andi(u8 rd, u8 rs1, u16 imm11_0) argument 352 rv_ori(u8 rd, u8 rs1, u16 imm11_0) argument 357 rv_xori(u8 rd, u8 rs1, u16 imm11_0) argument 362 rv_slli(u8 rd, u8 rs1, u16 imm11_0) argument 367 rv_srli(u8 rd, u8 rs1, u16 imm11_0) argument 372 rv_srai(u8 rd, u8 rs1, u16 imm11_0) argument 387 rv_add(u8 rd, u8 rs1, u8 rs2) argument 392 rv_sub(u8 rd, u8 rs1, u8 rs2) argument 397 rv_sltu(u8 rd, u8 rs1, u8 rs2) argument 402 rv_and(u8 rd, u8 rs1, u8 rs2) argument 407 rv_or(u8 rd, u8 rs1, u8 rs2) argument 412 rv_xor(u8 rd, u8 rs1, u8 rs2) argument 417 rv_sll(u8 rd, u8 rs1, u8 rs2) argument 422 rv_srl(u8 rd, u8 rs1, u8 rs2) argument 427 rv_sra(u8 rd, u8 rs1, u8 rs2) argument 432 rv_mul(u8 rd, u8 rs1, u8 rs2) argument 437 rv_mulhu(u8 rd, u8 rs1, u8 rs2) argument 442 rv_div(u8 rd, u8 rs1, u8 rs2) argument 447 rv_divu(u8 rd, u8 rs1, u8 rs2) argument 452 rv_rem(u8 rd, u8 rs1, u8 rs2) argument 457 rv_remu(u8 rd, u8 rs1, u8 rs2) argument 467 rv_jalr(u8 rd, u8 rs1, u16 imm11_0) argument 472 rv_beq(u8 rs1, u8 rs2, u16 imm12_1) argument 477 rv_bne(u8 rs1, u8 rs2, u16 imm12_1) argument 482 rv_bltu(u8 rs1, u8 rs2, u16 imm12_1) argument 487 rv_bgtu(u8 rs1, u8 rs2, u16 imm12_1) argument 492 rv_bgeu(u8 rs1, u8 rs2, u16 imm12_1) argument 497 rv_bleu(u8 rs1, u8 rs2, u16 imm12_1) argument 502 rv_blt(u8 rs1, u8 rs2, u16 imm12_1) argument 507 rv_bgt(u8 rs1, u8 rs2, u16 imm12_1) argument 512 rv_bge(u8 rs1, u8 rs2, u16 imm12_1) argument 517 rv_ble(u8 rs1, u8 rs2, u16 imm12_1) argument 522 rv_lb(u8 rd, u16 imm11_0, u8 rs1) argument 527 rv_lh(u8 rd, u16 imm11_0, u8 rs1) argument 532 rv_lw(u8 rd, u16 imm11_0, u8 rs1) argument 537 rv_lbu(u8 rd, u16 imm11_0, u8 rs1) argument 542 rv_lhu(u8 rd, u16 imm11_0, u8 rs1) argument 547 rv_sb(u8 rs1, u16 imm11_0, u8 rs2) argument 552 rv_sh(u8 rs1, u16 imm11_0, u8 rs2) argument 557 rv_sw(u8 rs1, u16 imm11_0, u8 rs2) argument 562 rv_amoadd_w(u8 rd, u8 rs2, u8 rs1, u8 aq, u8 rl) argument 567 rv_amoand_w(u8 rd, u8 rs2, u8 rs1, u8 aq, u8 rl) argument 572 rv_amoor_w(u8 rd, u8 rs2, u8 rs1, u8 aq, u8 rl) argument 577 rv_amoxor_w(u8 rd, u8 rs2, u8 rs1, u8 aq, u8 rl) argument 582 rv_amoswap_w(u8 rd, u8 rs2, u8 rs1, u8 aq, u8 rl) argument 587 rv_lr_w(u8 rd, u8 rs2, u8 rs1, u8 aq, u8 rl) argument 592 rv_sc_w(u8 rd, u8 rs2, u8 rs1, u8 aq, u8 rl) argument 620 rvc_lw(u8 rd, u32 imm7, u8 rs1) argument 629 rvc_sw(u8 rs1, u32 imm7, u8 rs2) argument 710 rvc_jr(u8 rs1) argument 720 rvc_jalr(u8 rs1) argument 739 rvzbb_sextb(u8 rd, u8 rs1) argument 744 rvzbb_sexth(u8 rd, u8 rs1) argument 774 rv_addiw(u8 rd, u8 rs1, u16 imm11_0) argument 779 rv_slliw(u8 rd, u8 rs1, u16 imm11_0) argument 784 rv_srliw(u8 rd, u8 rs1, u16 imm11_0) argument 789 rv_sraiw(u8 rd, u8 rs1, u16 imm11_0) argument 794 rv_addw(u8 rd, u8 rs1, u8 rs2) argument 799 rv_subw(u8 rd, u8 rs1, u8 rs2) argument 804 rv_sllw(u8 rd, u8 rs1, u8 rs2) argument 809 rv_srlw(u8 rd, u8 rs1, u8 rs2) argument 814 rv_sraw(u8 rd, u8 rs1, u8 rs2) argument 819 rv_mulw(u8 rd, u8 rs1, u8 rs2) argument 824 rv_divw(u8 rd, u8 rs1, u8 rs2) argument 829 rv_divuw(u8 rd, u8 rs1, u8 rs2) argument 834 rv_remw(u8 rd, u8 rs1, u8 rs2) argument 839 rv_remuw(u8 rd, u8 rs1, u8 rs2) argument 844 rv_ld(u8 rd, u16 imm11_0, u8 rs1) argument 849 rv_lwu(u8 rd, u16 imm11_0, u8 rs1) argument 854 rv_sd(u8 rs1, u16 imm11_0, u8 rs2) argument 859 rv_amoadd_d(u8 rd, u8 rs2, u8 rs1, u8 aq, u8 rl) argument 864 rv_amoand_d(u8 rd, u8 rs2, u8 rs1, u8 aq, u8 rl) argument 869 rv_amoor_d(u8 rd, u8 rs2, u8 rs1, u8 aq, u8 rl) argument 874 rv_amoxor_d(u8 rd, u8 rs2, u8 rs1, u8 aq, u8 rl) argument 879 rv_amoswap_d(u8 rd, u8 rs2, u8 rs1, u8 aq, u8 rl) argument 884 rv_lr_d(u8 rd, u8 rs2, u8 rs1, u8 aq, u8 rl) argument 889 rv_sc_d(u8 rd, u8 rs2, u8 rs1, u8 aq, u8 rl) argument 896 rvc_ld(u8 rd, u32 imm8, u8 rs1) argument 905 rvc_sd(u8 rs1, u32 imm8, u8 rs2) argument 962 emit_add(u8 rd, u8 rs1, u8 rs2, struct rv_jit_context ctx) argument 1031 emit_sub(u8 rd, u8 rs1, u8 rs2, struct rv_jit_context ctx) argument 1039 emit_or(u8 rd, u8 rs1, u8 rs2, struct rv_jit_context ctx) argument 1047 emit_and(u8 rd, u8 rs1, u8 rs2, struct rv_jit_context ctx) argument 1055 emit_xor(u8 rd, u8 rs1, u8 rs2, struct rv_jit_context ctx) argument 1063 emit_lw(u8 rd, s32 off, u8 rs1, struct rv_jit_context ctx) argument 1073 emit_sw(u8 rs1, s32 off, u8 rs2, struct rv_jit_context ctx) argument 1094 emit_ld(u8 rd, s32 off, u8 rs1, struct rv_jit_context ctx) argument 1104 emit_sd(u8 rs1, s32 off, u8 rs2, struct rv_jit_context ctx) argument 1114 emit_subw(u8 rd, u8 rs1, u8 rs2, struct rv_jit_context ctx) argument [all...]
H A D	bpf_jit_comp32.c	571 const s8 rs1 = bpf_get_reg64(src1, tmp1, ctx); local 587 emit(rv_bne(hi(rs1), hi(rs2), NO_JUMP(1)), ctx); 588 emit(rv_bne(lo(rs1), lo(rs2), NO_JUMP(0)), ctx); 591 emit(rv_bgtu(hi(rs1), hi(rs2), JUMP(2)), ctx); 592 emit(rv_bltu(hi(rs1), hi(rs2), NO_JUMP(1)), ctx); 593 emit(rv_bleu(lo(rs1), lo(rs2), NO_JUMP(0)), ctx); 596 emit(rv_bltu(hi(rs1), hi(rs2), JUMP(2)), ctx); 597 emit(rv_bgtu(hi(rs1), hi(rs2), NO_JUMP(1)), ctx); 598 emit(rv_bgeu(lo(rs1), lo(rs2), NO_JUMP(0)), ctx); 601 emit(rv_bgtu(hi(rs1), h 729 const s8 rs1 = bpf_get_reg32(src1, tmp1, ctx); local [all...]
/linux-master/arch/riscv/include/asm/
H A D	insn-def.h	25 .macro insn_r, opcode, func3, func7, rd, rs1, rs2 variable 26 .insn r \opcode, \func3, \func7, \rd, \rs1, \rs2 variable 29 .macro insn_i, opcode, func3, rd, rs1, simm12 variable 30 .insn i \opcode, \func3, \rd, \rs1, \simm12 variable 37 .macro insn_r, opcode, func3, func7, rd, rs1, rs2 42 (.L__gpr_num_\rs1 << INSN_R_RS1_SHIFT) \| \ 46 .macro insn_i, opcode, func3, rd, rs1, simm12 50 (.L__gpr_num_\rs1 << INSN_I_RS1_SHIFT) \| \ 63 #define __INSN_R(opcode, func3, func7, rd, rs1, rs2) \ 64 ".insn r " opcode ", " func3 ", " func7 ", " rd ", " rs1 ", " rs [all...]
/linux-master/arch/sparc/kernel/
H A D	visemul.c	140 static inline void maybe_flush_windows(unsigned int rs1, unsigned int rs2, argument 143 if (rs2 >= 16 \|\| rs1 >= 16 \|\| rd >= 16) { 296 unsigned long orig_rs1, rs1, orig_rs2, rs2, rd_val; local 300 orig_rs1 = rs1 = fetch_reg(RS1(insn), regs); 304 rs1 = rs1 & 0xffffffff; 311 left = edge8_tab[rs1 & 0x7].left; 316 left = edge8_tab_l[rs1 & 0x7].left; 322 left = edge16_tab[(rs1 >> 1) & 0x3].left; 328 left = edge16_tab_l[(rs1 >> 374 unsigned long rs1, rs2, rd_val; local 408 unsigned long rs1, rs2, rd_val, gsr; local 425 unsigned long rs1, rs2, rd_val; local 451 unsigned long rs1, rs2, *rd, rd_val; local 480 unsigned long rs1, rs2, gsr, scale, rd_val; local 592 unsigned long rs1, rs2, rd_val; local 708 unsigned long rs1, rs2, rd_val, i; local [all...]
H A D	unaligned_32.c	72 static inline void maybe_flush_windows(unsigned int rs1, unsigned int rs2, argument 75 if(rs2 >= 16 \|\| rs1 >= 16 \|\| rd >= 16) { 139 unsigned int rs1 = (insn >> 14) & 0x1f; local 144 maybe_flush_windows(rs1, 0, rd); 145 return (fetch_reg(rs1, regs) + sign_extend_imm13(insn)); 147 maybe_flush_windows(rs1, rs2, rd); 148 return (fetch_reg(rs1, regs) + fetch_reg(rs2, regs)); 155 unsigned int rs1 = (insn >> 14) & 0x1f; local 160 maybe_flush_windows(rs1, 0, rd); 161 return (safe_fetch_reg(rs1, reg [all...]
H A D	unaligned_64.c	`104 static inline void maybe_flush_windows(unsigned int rs1, unsigned int rs2, argument 107 if (rs2 >= 16 \|\| rs1 >= 16 \|\| rd >= 16) { 173 unsigned int rs1 = (insn >> 14) & 0x1f; local 178 maybe_flush_windows(rs1, 0, rd, from_kernel); 179 addr = (fetch_reg(rs1, regs) + sign_extend_imm13(insn)); 181 maybe_flush_windows(rs1, rs2, rd, from_kernel); 182 addr = (fetch_reg(rs1, regs) + fetch_reg(rs2, regs));`
/linux-master/arch/arm/kernel/
H A D	sleep.S	`16 * @rs1: register containing affinity level 1 bit shift 25 compute_mpidr_hash(u32 rs0, u32 rs1, u32 rs2, u32 mpidr, u32 mask) { 31 dst = (aff0 >> rs0 \| aff1 >> rs1 \| aff2 >> rs2); 33 * Input registers: rs0, rs1, rs2, mpidr, mask 38 .macro compute_mpidr_hash dst, rs0, rs1, rs2, mpidr, mask 44 ARM( orr \dst, \dst, \mask, lsr \rs1 ) @ dst\|=(aff1>>rs1) 45 THUMB( lsr \mask, \mask, \rs1 )`
/linux-master/arch/riscv/kernel/probes/
H A D	simulate-insn.c	65 * offset[11:0] \| rs1 \| 010 \| rd \| opcode 144 * \| imm[12] \| imm[10:5] \| rs2 \| rs1 \| funct3 \| imm[4:1] \| imm[11] \| opcode \| 146 * imm[12\|10:5] rs2 rs1 000 imm[4:1\|11] 1100011 BEQ 147 * imm[12\|10:5] rs2 rs1 001 imm[4:1\|11] 1100011 BNE 148 * imm[12\|10:5] rs2 rs1 100 imm[4:1\|11] 1100011 BLT 149 * imm[12\|10:5] rs2 rs1 101 imm[4:1\|11] 1100011 BGE 150 * imm[12\|10:5] rs2 rs1 110 imm[4:1\|11] 1100011 BLTU 151 * imm[12\|10:5] rs2 rs1 111 imm[4:1\|11] 1100011 BGEU 221 * \| funct4 \| rs1 \| rs2 \| op \| 227 u32 rs1 local 263 u32 rs1; local [all...]
/linux-master/arch/parisc/net/
H A D	bpf_jit_comp32.c	706 const s8 rs1 = bpf_get_reg64(src1, tmp1, ctx); local 722 emit(hppa_bne(hi(rs1), hi(rs2), NO_JUMP(1)), ctx); 723 emit(hppa_bne(lo(rs1), lo(rs2), NO_JUMP(0)), ctx); 726 emit(hppa_bgtu(hi(rs1), hi(rs2), JUMP(2)), ctx); 727 emit(hppa_bltu(hi(rs1), hi(rs2), NO_JUMP(1)), ctx); 728 emit(hppa_bleu(lo(rs1), lo(rs2), NO_JUMP(0)), ctx); 731 emit(hppa_bltu(hi(rs1), hi(rs2), JUMP(2)), ctx); 732 emit(hppa_bgtu(hi(rs1), hi(rs2), NO_JUMP(1)), ctx); 733 emit(hppa_bgeu(lo(rs1), lo(rs2), NO_JUMP(0)), ctx); 736 emit(hppa_bgtu(hi(rs1), h 873 const s8 rs1 = bpf_get_reg32(src1, tmp1, ctx); local [all...]
/linux-master/arch/arm64/kernel/
H A D	sleep.S	`15 * @rs1: register containing affinity level 1 bit shift 25 compute_mpidr_hash(u32 rs0, u32 rs1, u32 rs2, u32 rs3, u64 mpidr, u64 mask) { 32 dst = (aff0 >> rs0 \| aff1 >> rs1 \| aff2 >> rs2 \| aff3 >> rs3); 34 * Input registers: rs0, rs1, rs2, rs3, mpidr, mask 39 .macro compute_mpidr_hash dst, rs0, rs1, rs2, rs3, mpidr, mask 44 lsr \mask ,\mask, \rs1 45 orr \dst, \dst, \mask // dst\|=(aff1>>rs1)`
/linux-master/arch/sparc/math-emu/
H A D	math_32.c	`279 /* r is rd, b is rs2 and a is rs1. The u arg tells 284 argp rs1 = NULL, rs2 = NULL, rd = NULL; local 355 switch (type & 0x3) { / is rs1 single, double or quad? */ 369 rs1 = (argp)&fregs[freg]; 371 case 7: FP_UNPACK_QP (QA, rs1); break; 372 case 6: FP_UNPACK_DP (DA, rs1); break; 373 case 5: FP_UNPACK_SP (SA, rs1); break;`
H A D	math_64.c	`173 /* ftt tells which ftt it may happen in, r is rd, b is rs2 and a is rs1. The *u arg tells 359 argp rs1 = NULL, rs2 = NULL, rd = NULL; local 380 case 1: rs1 = (argp)&f->regs[freg]; 383 rs1 = (argp)&zero; 387 case 7: FP_UNPACK_QP (QA, rs1); break; 388 case 6: FP_UNPACK_DP (DA, rs1); break; 389 case 5: FP_UNPACK_SP (SA, rs1); break;`
/linux-master/arch/mips/crypto/
H A D	poly1305-mips.pl	`226 my ($h0,$h1,$h2,$r0,$r1,$rs1,$d0,$d1,$d2) = 283 ld $rs1,40($ctx) 380 dmultu ($rs1,$d1) # h15r1 383 mflo ($tmp0,$rs1,$d1) 384 mfhi ($tmp1,$rs1,$d1) 399 dmultu ($rs1,$d2) # h25r1 402 mflo ($tmp2,$rs1,$d2) 733 my ($h0,$h1,$h2,$h3,$h4, $r0,$r1,$r2,$r3, $rs1,$rs2,$rs3) = 787 lw $rs1,36($ctx) 927 maddu $rs1, [all...]`
/linux-master/drivers/edac/
H A D	pnd2_edac.h	`224 u32 rs1 : 5; member in struct:d_cr_dmap`
H A D	pnd2_edac.c	`981 daddr->rank \|= dnv_get_bit(pmiaddr, dmap[pmiidx].rs1 + 13, 1);`

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