/linux-master/drivers/power/supply/ |
H A D | max17040_battery.c | 56 u16 reset_val; member in struct:chip_data 67 .reset_val = 0x0054, 76 .reset_val = 0x0054, 85 .reset_val = 0x0054, 94 .reset_val = 0x0054, 103 .reset_val = 0x5400, 112 .reset_val = 0x5400, 121 .reset_val = 0x5400, 130 .reset_val = 0x5400, 160 return regmap_write(chip->regmap, MAX17040_CMD, chip->data.reset_val); [all...] |
H A D | cw2015_battery.c | 101 u8 reset_val; local 108 reset_val = reg_val; 131 reset_val &= ~CW2015_MODE_RESTART; 132 reg_val = reset_val | CW2015_MODE_RESTART; 141 ret = regmap_write(cw_bat->regmap, CW2015_REG_MODE, reset_val); 230 unsigned char reset_val; local 232 reset_val = CW2015_MODE_SLEEP; 233 ret = regmap_write(cw_bat->regmap, CW2015_REG_MODE, reset_val); 240 reset_val = CW2015_MODE_NORMAL; 241 ret = regmap_write(cw_bat->regmap, CW2015_REG_MODE, reset_val); [all...] |
/linux-master/arch/arm64/kvm/ |
H A D | sys_regs.c | 2202 { SYS_DESC(SYS_MDCCINT_EL1), trap_debug_regs, reset_val, MDCCINT_EL1, 0 }, 2203 { SYS_DESC(SYS_MDSCR_EL1), trap_debug_regs, reset_val, MDSCR_EL1, 0 }, 2221 { SYS_DESC(SYS_OSLSR_EL1), trap_oslsr_el1, reset_val, OSLSR_EL1, 2234 { SYS_DESC(SYS_DBGVCR32_EL2), trap_undef, reset_val, DBGVCR32_EL2, 0 }, 2358 { SYS_DESC(SYS_SCTLR_EL1), access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 }, 2360 { SYS_DESC(SYS_CPACR_EL1), NULL, reset_val, CPACR_EL1, 0 }, 2365 { SYS_DESC(SYS_ZCR_EL1), NULL, reset_val, ZCR_EL1, 0, .visibility = sve_visibility }, 2371 { SYS_DESC(SYS_TCR_EL1), access_vm_reg, reset_val, TCR_EL1, 0 }, 2372 { SYS_DESC(SYS_TCR2_EL1), access_vm_reg, reset_val, TCR2_EL1, 0 }, 2434 { SYS_DESC(SYS_VBAR_EL1), access_rw, reset_val, VBAR_EL [all...] |
H A D | sys_regs.h | 145 static inline u64 reset_val(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) function
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/linux-master/drivers/memory/ |
H A D | stm32-fmc2-ebi.c | 217 * @reset_val: the default value that have to be set in case the property 232 u32 reset_val; member in struct:stm32_fmc2_prop 948 .reset_val = FMC2_BUSWIDTH_16, 995 .reset_val = FMC2_BXTR_ADDSET_MAX, 1003 .reset_val = FMC2_BXTR_ADDHLD_MAX, 1011 .reset_val = FMC2_BXTR_DATAST_MAX, 1019 .reset_val = FMC2_BXTR_BUSTURN_MAX + 1, 1032 .reset_val = FMC2_BTR_CLKDIV_MAX + 1, 1046 .reset_val = FMC2_BXTR_ADDSET_MAX, 1054 .reset_val [all...] |
/linux-master/include/linux/qed/ |
H A D | qed_chain.h | 498 u32 reset_val = p_chain->page_cnt - 1; local 501 p_chain->pbl.c.u16.prod_page_idx = (u16)reset_val; 502 p_chain->pbl.c.u16.cons_page_idx = (u16)reset_val; 504 p_chain->pbl.c.u32.prod_page_idx = reset_val; 505 p_chain->pbl.c.u32.cons_page_idx = reset_val;
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/linux-master/drivers/gpu/drm/amd/display/dc/dcn32/ |
H A D | dcn32_dio_stream_encoder.c | 431 uint32_t reset_val = reset ? 1 : 0; local 434 REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_RESET, reset_val); 438 REG_WAIT(DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, reset_val, 10, 5000);
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/linux-master/drivers/gpu/drm/amd/display/dc/dcn314/ |
H A D | dcn314_dio_stream_encoder.c | 55 uint32_t reset_val = reset ? 1 : 0; local 58 REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_RESET, reset_val); 62 REG_WAIT(DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, reset_val, 10, 5000);
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/linux-master/drivers/gpu/drm/amd/display/dc/dcn35/ |
H A D | dcn35_dio_stream_encoder.c | 416 uint32_t reset_val = reset ? 1 : 0; local 419 REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_RESET, reset_val); 423 REG_WAIT(DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, reset_val, 10, 5000);
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/linux-master/drivers/net/ethernet/amd/ |
H A D | lance.c | 475 int i, reset_val, lance_version; local 508 reset_val = inw(ioaddr+LANCE_RESET); /* Reset the LANCE */ 513 outw(reset_val, ioaddr+LANCE_RESET); 604 short reset_val = inw(ioaddr+LANCE_RESET); local 605 dev->dma = dma_tbl[(reset_val >> 2) & 3]; 606 dev->irq = irq_tbl[(reset_val >> 4) & 7];
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/linux-master/drivers/infiniband/hw/efa/ |
H A D | efa_com.c | 1043 u32 reset_val = 0; local 1062 EFA_SET(&reset_val, EFA_REGS_DEV_CTL_DEV_RESET, 1); 1063 EFA_SET(&reset_val, EFA_REGS_DEV_CTL_RESET_REASON, reset_reason); 1064 writel(reset_val, edev->reg_bar + EFA_REGS_DEV_CTL_OFF);
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/linux-master/drivers/scsi/hisi_sas/ |
H A D | hisi_sas_v2_hw.c | 1018 int i, reset_val; local 1025 reset_val = 0x1fffff; 1027 reset_val = 0x7ffff; 1087 reset_val); 1089 reset_val); 1092 if (reset_val != (val & reset_val)) { 1099 reset_val); 1101 reset_val); 1105 if (val & reset_val) { [all...] |
/linux-master/drivers/gpu/drm/msm/adreno/ |
H A D | a6xx_gmu.c | 208 u32 mask, reset_val, val; local 214 reset_val = 0xbabeface; 217 reset_val = 0x100; 234 (val & mask) == reset_val, 100, 10000);
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/linux-master/drivers/net/ethernet/amazon/ena/ |
H A D | ena_com.c | 2060 u32 stat, timeout, cap, reset_val; local 2084 reset_val = ENA_REGS_DEV_CTL_DEV_RESET_MASK; 2085 reset_val |= (reset_reason << ENA_REGS_DEV_CTL_RESET_REASON_SHIFT) & 2087 writel(reset_val, ena_dev->reg_bar + ENA_REGS_DEV_CTL_OFF);
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/linux-master/drivers/gpu/drm/bridge/ |
H A D | samsung-dsim.c | 554 u32 reset_val = dsi->driver_data->reg_values[RESET_TYPE]; local 557 samsung_dsim_write(dsi, DSIM_SWRST_REG, reset_val);
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/linux-master/drivers/usb/cdns3/ |
H A D | cdns3-gadget.c | 715 u16 reset_val = EP_CMD_TDL_MAX + 1 - tdl; local 717 writel(EP_CMD_TDL_SET(reset_val) | EP_CMD_STDL,
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/linux-master/drivers/net/ethernet/sun/ |
H A D | niu.c | 932 u64 reset_val, val_rd; local 939 reset_val = ENET_SERDES_RESET_0; 945 reset_val = ENET_SERDES_RESET_1; 979 nw64(ENET_SERDES_RESET, reset_val); 982 val_rd &= ~reset_val;
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/linux-master/drivers/net/ethernet/qlogic/qed/ |
H A D | qed_debug.c | 286 u32 reset_val[MAX_CHIP_IDS]; member in struct:rbc_reset_defs 1701 if (s_rbc_reset_defs[i].reset_val[dev_data->chip_id]) 1706 s_rbc_reset_defs[i].reset_val[chip_id]);
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