Lines Matching refs:reset_val
2216 { SYS_DESC(SYS_MDCCINT_EL1), trap_debug_regs, reset_val, MDCCINT_EL1, 0 },
2217 { SYS_DESC(SYS_MDSCR_EL1), trap_debug_regs, reset_val, MDSCR_EL1, 0 },
2235 { SYS_DESC(SYS_OSLSR_EL1), trap_oslsr_el1, reset_val, OSLSR_EL1,
2248 { SYS_DESC(SYS_DBGVCR32_EL2), trap_undef, reset_val, DBGVCR32_EL2, 0 },
2371 { SYS_DESC(SYS_SCTLR_EL1), access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 },
2373 { SYS_DESC(SYS_CPACR_EL1), NULL, reset_val, CPACR_EL1, 0 },
2378 { SYS_DESC(SYS_ZCR_EL1), NULL, reset_val, ZCR_EL1, 0, .visibility = sve_visibility },
2384 { SYS_DESC(SYS_TCR_EL1), access_vm_reg, reset_val, TCR_EL1, 0 },
2385 { SYS_DESC(SYS_TCR2_EL1), access_vm_reg, reset_val, TCR2_EL1, 0 },
2447 { SYS_DESC(SYS_VBAR_EL1), access_rw, reset_val, VBAR_EL1, 0 },
2448 { SYS_DESC(SYS_DISR_EL1), NULL, reset_val, DISR_EL1, 0 },
2463 { SYS_DESC(SYS_CONTEXTIDR_EL1), access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 },
2470 { SYS_DESC(SYS_CNTKCTL_EL1), NULL, reset_val, CNTKCTL_EL1, 0},
2517 .reset = reset_val, .reg = PMUSERENR_EL0, .val = 0 },
2676 .reset = reset_val, .reg = PMCCFILTR_EL0, .val = 0 },
2680 EL2_REG(SCTLR_EL2, access_rw, reset_val, SCTLR_EL2_RES1),
2681 EL2_REG(ACTLR_EL2, access_rw, reset_val, 0),
2683 EL2_REG(MDCR_EL2, access_rw, reset_val, 0),
2684 EL2_REG(CPTR_EL2, access_rw, reset_val, CPTR_NVHE_EL2_RES1),
2685 EL2_REG_VNCR(HSTR_EL2, reset_val, 0),
2686 EL2_REG_VNCR(HFGRTR_EL2, reset_val, 0),
2687 EL2_REG_VNCR(HFGWTR_EL2, reset_val, 0),
2688 EL2_REG_VNCR(HFGITR_EL2, reset_val, 0),
2689 EL2_REG_VNCR(HACR_EL2, reset_val, 0),
2691 EL2_REG_VNCR(HCRX_EL2, reset_val, 0),
2693 EL2_REG(TTBR0_EL2, access_rw, reset_val, 0),
2694 EL2_REG(TTBR1_EL2, access_rw, reset_val, 0),
2695 EL2_REG(TCR_EL2, access_rw, reset_val, TCR_EL2_RES1),
2696 EL2_REG_VNCR(VTTBR_EL2, reset_val, 0),
2697 EL2_REG_VNCR(VTCR_EL2, reset_val, 0),
2700 EL2_REG_VNCR(HDFGRTR_EL2, reset_val, 0),
2701 EL2_REG_VNCR(HDFGWTR_EL2, reset_val, 0),
2702 EL2_REG_VNCR(HAFGRTR_EL2, reset_val, 0),
2703 EL2_REG_REDIR(SPSR_EL2, reset_val, 0),
2704 EL2_REG_REDIR(ELR_EL2, reset_val, 0),
2718 EL2_REG(AFSR0_EL2, access_rw, reset_val, 0),
2719 EL2_REG(AFSR1_EL2, access_rw, reset_val, 0),
2720 EL2_REG_REDIR(ESR_EL2, reset_val, 0),
2721 { SYS_DESC(SYS_FPEXC32_EL2), trap_undef, reset_val, FPEXC32_EL2, 0x700 },
2723 EL2_REG_REDIR(FAR_EL2, reset_val, 0),
2724 EL2_REG(HPFAR_EL2, access_rw, reset_val, 0),
2726 EL2_REG(MAIR_EL2, access_rw, reset_val, 0),
2727 EL2_REG(AMAIR_EL2, access_rw, reset_val, 0),
2729 EL2_REG(VBAR_EL2, access_rw, reset_val, 0),
2730 EL2_REG(RVBAR_EL2, access_rw, reset_val, 0),
2733 EL2_REG(CONTEXTIDR_EL2, access_rw, reset_val, 0),
2734 EL2_REG(TPIDR_EL2, access_rw, reset_val, 0),
2736 EL2_REG_VNCR(CNTVOFF_EL2, reset_val, 0),
2737 EL2_REG(CNTHCTL_EL2, access_rw, reset_val, 0),
2739 EL12_REG(CNTKCTL, access_rw, reset_val, 0),