Searched refs:reset_lock (Results 1 - 25 of 25) sorted by relevance

/linux-master/drivers/pci/hotplug/
H A Dpciehp_pci.c68 * Release reset_lock during driver binding
71 up_read(&ctrl->reset_lock);
73 down_read_nested(&ctrl->reset_lock, ctrl->depth);
116 * Release reset_lock during driver unbinding
119 up_read(&ctrl->reset_lock);
121 down_read_nested(&ctrl->reset_lock, ctrl->depth);
H A Dpciehp_core.c170 down_read_nested(&ctrl->reset_lock, ctrl->depth);
181 up_read(&ctrl->reset_lock);
H A Dpciehp_hpc.c583 down_read_nested(&ctrl->reset_lock, ctrl->depth);
586 up_read(&ctrl->reset_lock);
744 down_read_nested(&ctrl->reset_lock, ctrl->depth);
749 up_read(&ctrl->reset_lock);
906 down_write_nested(&ctrl->reset_lock, ctrl->depth);
926 up_write(&ctrl->reset_lock);
1005 init_rwsem(&ctrl->reset_lock);
H A Dpciehp.h75 * @reset_lock: prevents access to the Data Link Layer Link Active bit in the
79 * used as lock subclass for @reset_lock
110 struct rw_semaphore reset_lock; member in struct:controller
/linux-master/drivers/clk/mmp/
H A Dclk-of-pxa1928.c96 static DEFINE_SPINLOCK(reset_lock);
108 {PXA1928_CLK_TWSI0, "twsi0_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_TWSI0 * 4, 0x3, 0x3, 0x0, 0, &reset_lock},
109 {PXA1928_CLK_TWSI1, "twsi1_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_TWSI1 * 4, 0x3, 0x3, 0x0, 0, &reset_lock},
110 {PXA1928_CLK_TWSI2, "twsi2_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_TWSI2 * 4, 0x3, 0x3, 0x0, 0, &reset_lock},
111 {PXA1928_CLK_TWSI3, "twsi3_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_TWSI3 * 4, 0x3, 0x3, 0x0, 0, &reset_lock},
112 {PXA1928_CLK_TWSI4, "twsi4_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_TWSI4 * 4, 0x3, 0x3, 0x0, 0, &reset_lock},
113 {PXA1928_CLK_TWSI5, "twsi5_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_TWSI5 * 4, 0x3, 0x3, 0x0, 0, &reset_lock},
114 {PXA1928_CLK_GPIO, "gpio_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_GPIO * 4, 0x3, 0x3, 0x0, 0, &reset_lock},
117 {PXA1928_CLK_PWM0, "pwm0_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_PWM0 * 4, 0x3, 0x3, 0x0, 0, &reset_lock},
118 {PXA1928_CLK_PWM1, "pwm1_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_PWM1 * 4, 0x3, 0x3, 0x0, 0, &reset_lock},
[all...]
H A Dclk-of-mmp2.c236 static DEFINE_SPINLOCK(reset_lock);
251 {MMP2_CLK_TWSI0, "twsi0_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_TWSI0, 0x7, 0x3, 0x0, 0, &reset_lock},
252 {MMP2_CLK_TWSI1, "twsi1_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_TWSI1, 0x7, 0x3, 0x0, 0, &reset_lock},
253 {MMP2_CLK_TWSI2, "twsi2_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_TWSI2, 0x7, 0x3, 0x0, 0, &reset_lock},
254 {MMP2_CLK_TWSI3, "twsi3_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_TWSI3, 0x7, 0x3, 0x0, 0, &reset_lock},
255 {MMP2_CLK_TWSI4, "twsi4_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_TWSI4, 0x7, 0x3, 0x0, 0, &reset_lock},
256 {MMP2_CLK_TWSI5, "twsi5_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_TWSI5, 0x7, 0x3, 0x0, 0, &reset_lock},
257 {MMP2_CLK_GPIO, "gpio_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_GPIO, 0x7, 0x3, 0x0, 0, &reset_lock},
258 {MMP2_CLK_KPC, "kpc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_KPC, 0x7, 0x3, 0x0, MMP_CLK_GATE_NEED_DELAY, &reset_lock},
259 {MMP2_CLK_RTC, "rtc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_RTC, 0x87, 0x83, 0x0, MMP_CLK_GATE_NEED_DELAY, &reset_lock},
[all...]
H A Dclk-of-pxa910.c125 static DEFINE_SPINLOCK(reset_lock);
141 {PXA910_CLK_TWSI0, "twsi0_clk", "pll1_13_1_5", CLK_SET_RATE_PARENT, APBC_TWSI0, 0x3, 0x3, 0x0, 0, &reset_lock},
142 {PXA910_CLK_GPIO, "gpio_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_GPIO, 0x3, 0x3, 0x0, 0, &reset_lock},
145 {PXA910_CLK_PWM0, "pwm0_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM0, 0x3, 0x3, 0x0, 0, &reset_lock},
146 {PXA910_CLK_PWM1, "pwm1_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM1, 0x3, 0x3, 0x0, 0, &reset_lock},
147 {PXA910_CLK_PWM2, "pwm2_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM2, 0x3, 0x3, 0x0, 0, &reset_lock},
148 {PXA910_CLK_PWM3, "pwm3_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM3, 0x3, 0x3, 0x0, 0, &reset_lock},
159 {PXA910_CLK_TWSI1, "twsi1_clk", "pll1_13_1_5", CLK_SET_RATE_PARENT, APBCP_TWSI1, 0x3, 0x3, 0x0, 0, &reset_lock},
H A Dclk-of-pxa168.c160 static DEFINE_SPINLOCK(reset_lock);
184 {PXA168_CLK_GPIO, "gpio_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_GPIO, 0x1, 0x1, 0x0, 0, &reset_lock},
/linux-master/drivers/accel/ivpu/
H A Divpu_pm.h18 struct rw_semaphore reset_lock; member in struct:ivpu_pm_info
H A Divpu_pm.c129 down_write(&vdev->pm->reset_lock);
139 up_write(&vdev->pm->reset_lock);
331 down_write(&vdev->pm->reset_lock);
348 up_write(&vdev->pm->reset_lock);
365 init_rwsem(&pm->reset_lock);
H A Divpu_job.c528 down_read(&vdev->pm->reset_lock);
530 up_read(&vdev->pm->reset_lock);
/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_reset.h65 struct mutex reset_lock; member in struct:amdgpu_reset_control
H A Daldebaran.c164 mutex_lock(&tmp_adev->reset_cntl->reset_lock);
200 mutex_unlock(&tmp_adev->reset_cntl->reset_lock);
/linux-master/drivers/hid/i2c-hid/
H A Di2c-hid-core.c108 struct mutex reset_lock; member in struct:i2c_hid
434 lockdep_assert_held(&ihid->reset_lock);
665 mutex_lock(&ihid->reset_lock);
681 mutex_unlock(&ihid->reset_lock);
726 mutex_lock(&ihid->reset_lock);
734 mutex_unlock(&ihid->reset_lock);
971 mutex_lock(&ihid->reset_lock);
975 mutex_unlock(&ihid->reset_lock);
1193 mutex_init(&ihid->reset_lock);
/linux-master/drivers/net/ethernet/qualcomm/emac/
H A Demac.c84 mutex_lock(&adpt->reset_lock);
90 mutex_unlock(&adpt->reset_lock);
271 mutex_lock(&adpt->reset_lock);
279 mutex_unlock(&adpt->reset_lock);
626 mutex_init(&adpt->reset_lock);
H A Demac.h377 struct mutex reset_lock; member in struct:emac_adapter
/linux-master/drivers/net/ethernet/xilinx/
H A Dxilinx_emaclite.c111 * @reset_lock: lock to serialize xmit and tx_timeout execution
128 spinlock_t reset_lock; /* serialize xmit and tx_timeout execution */ member in struct:net_local
530 spin_lock_irqsave(&lp->reset_lock, flags);
549 spin_unlock_irqrestore(&lp->reset_lock, flags);
1007 spin_lock_irqsave(&lp->reset_lock, flags);
1017 spin_unlock_irqrestore(&lp->reset_lock, flags);
1020 spin_unlock_irqrestore(&lp->reset_lock, flags);
1126 spin_lock_init(&lp->reset_lock);
/linux-master/drivers/vfio/pci/mlx5/
H A Dmain.c1219 spin_lock(&mvdev->reset_lock);
1222 spin_unlock(&mvdev->reset_lock);
1228 spin_unlock(&mvdev->reset_lock);
1307 spin_lock(&mvdev->reset_lock);
1310 spin_unlock(&mvdev->reset_lock);
1313 spin_unlock(&mvdev->reset_lock);
H A Dcmd.h184 spinlock_t reset_lock; member in struct:mlx5vf_pci_core_device
H A Dcmd.c257 spin_lock_init(&mvdev->reset_lock);
/linux-master/drivers/gpu/drm/v3d/
H A Dv3d_gem.c261 ret = drmm_mutex_init(dev, &v3d->reset_lock);
H A Dv3d_drv.h147 struct mutex reset_lock; member in struct:v3d_dev
H A Dv3d_sched.c598 mutex_lock(&v3d->reset_lock);
618 mutex_unlock(&v3d->reset_lock);
/linux-master/drivers/scsi/
H A Dhpsa.h313 spinlock_t reset_lock; member in struct:ctlr_info
H A Dhpsa.c1937 spin_lock_irqsave(&h->reset_lock, flags);
1940 spin_unlock_irqrestore(&h->reset_lock, flags);
1943 spin_unlock_irqrestore(&h->reset_lock, flags);
5807 spin_lock_irqsave(&h->reset_lock, flags);
5810 spin_unlock_irqrestore(&h->reset_lock, flags);
5814 spin_unlock_irqrestore(&h->reset_lock, flags);
6039 spin_lock_irqsave(&h->reset_lock, flags);
6041 spin_unlock_irqrestore(&h->reset_lock, flags);
6119 spin_lock_irqsave(&h->reset_lock, flags);
6123 spin_unlock_irqrestore(&h->reset_lock, flag
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