1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * mmp2 clock framework source file 4 * 5 * Copyright (C) 2012 Marvell 6 * Chao Xie <xiechao.mail@gmail.com> 7 * Copyright (C) 2020 Lubomir Rintel <lkundrak@v3.sk> 8 */ 9 10#include <linux/module.h> 11#include <linux/kernel.h> 12#include <linux/spinlock.h> 13#include <linux/io.h> 14#include <linux/delay.h> 15#include <linux/err.h> 16#include <linux/of_address.h> 17#include <linux/clk.h> 18 19#include <dt-bindings/clock/marvell,mmp2.h> 20#include <dt-bindings/power/marvell,mmp2.h> 21 22#include "clk.h" 23#include "reset.h" 24 25#define APBC_RTC 0x0 26#define APBC_TWSI0 0x4 27#define APBC_TWSI1 0x8 28#define APBC_TWSI2 0xc 29#define APBC_TWSI3 0x10 30#define APBC_TWSI4 0x7c 31#define APBC_TWSI5 0x80 32#define APBC_KPC 0x18 33#define APBC_TIMER 0x24 34#define APBC_UART0 0x2c 35#define APBC_UART1 0x30 36#define APBC_UART2 0x34 37#define APBC_UART3 0x88 38#define APBC_GPIO 0x38 39#define APBC_PWM0 0x3c 40#define APBC_PWM1 0x40 41#define APBC_PWM2 0x44 42#define APBC_PWM3 0x48 43#define APBC_SSP0 0x50 44#define APBC_SSP1 0x54 45#define APBC_SSP2 0x58 46#define APBC_SSP3 0x5c 47#define APBC_THERMAL0 0x90 48#define APBC_THERMAL1 0x98 49#define APBC_THERMAL2 0x9c 50#define APBC_THERMAL3 0xa0 51#define APMU_SDH0 0x54 52#define APMU_SDH1 0x58 53#define APMU_SDH2 0xe8 54#define APMU_SDH3 0xec 55#define APMU_SDH4 0x15c 56#define APMU_USB 0x5c 57#define APMU_DISP0 0x4c 58#define APMU_DISP1 0x110 59#define APMU_CCIC0 0x50 60#define APMU_CCIC1 0xf4 61#define APMU_USBHSIC0 0xf8 62#define APMU_USBHSIC1 0xfc 63#define APMU_GPU 0xcc 64#define APMU_AUDIO 0x10c 65#define APMU_CAMERA 0x1fc 66 67#define MPMU_FCCR 0x8 68#define MPMU_POSR 0x10 69#define MPMU_UART_PLL 0x14 70#define MPMU_PLL2_CR 0x34 71#define MPMU_I2S0_PLL 0x40 72#define MPMU_I2S1_PLL 0x44 73#define MPMU_ACGR 0x1024 74/* MMP3 specific below */ 75#define MPMU_PLL3_CR 0x50 76#define MPMU_PLL3_CTRL1 0x58 77#define MPMU_PLL1_CTRL 0x5c 78#define MPMU_PLL_DIFF_CTRL 0x68 79#define MPMU_PLL2_CTRL1 0x414 80 81#define NR_CLKS 200 82 83enum mmp2_clk_model { 84 CLK_MODEL_MMP2, 85 CLK_MODEL_MMP3, 86}; 87 88struct mmp2_clk_unit { 89 struct mmp_clk_unit unit; 90 enum mmp2_clk_model model; 91 struct genpd_onecell_data pd_data; 92 struct generic_pm_domain *pm_domains[MMP2_NR_POWER_DOMAINS]; 93 void __iomem *mpmu_base; 94 void __iomem *apmu_base; 95 void __iomem *apbc_base; 96}; 97 98static struct mmp_param_fixed_rate_clk fixed_rate_clks[] = { 99 {MMP2_CLK_CLK32, "clk32", NULL, 0, 32768}, 100 {MMP2_CLK_VCTCXO, "vctcxo", NULL, 0, 26000000}, 101 {MMP2_CLK_USB_PLL, "usb_pll", NULL, 0, 480000000}, 102 {0, "i2s_pll", NULL, 0, 99666667}, 103}; 104 105static struct mmp_param_pll_clk pll_clks[] = { 106 {MMP2_CLK_PLL1, "pll1", 797330000, MPMU_FCCR, 0x4000, MPMU_POSR, 0}, 107 {MMP2_CLK_PLL2, "pll2", 0, MPMU_PLL2_CR, 0x0300, MPMU_PLL2_CR, 10}, 108}; 109 110static struct mmp_param_pll_clk mmp3_pll_clks[] = { 111 {MMP2_CLK_PLL2, "pll1", 797330000, MPMU_FCCR, 0x4000, MPMU_POSR, 0, 26000000, MPMU_PLL1_CTRL, 25}, 112 {MMP2_CLK_PLL2, "pll2", 0, MPMU_PLL2_CR, 0x0300, MPMU_PLL2_CR, 10, 26000000, MPMU_PLL2_CTRL1, 25}, 113 {MMP3_CLK_PLL1_P, "pll1_p", 0, MPMU_PLL_DIFF_CTRL, 0x0010, 0, 0, 797330000, MPMU_PLL_DIFF_CTRL, 0}, 114 {MMP3_CLK_PLL2_P, "pll2_p", 0, MPMU_PLL_DIFF_CTRL, 0x0100, MPMU_PLL2_CR, 10, 26000000, MPMU_PLL_DIFF_CTRL, 5}, 115 {MMP3_CLK_PLL3, "pll3", 0, MPMU_PLL3_CR, 0x0300, MPMU_PLL3_CR, 10, 26000000, MPMU_PLL3_CTRL1, 25}, 116}; 117 118static struct mmp_param_fixed_factor_clk fixed_factor_clks[] = { 119 {MMP2_CLK_PLL1_2, "pll1_2", "pll1", 1, 2, 0}, 120 {MMP2_CLK_PLL1_4, "pll1_4", "pll1_2", 1, 2, 0}, 121 {MMP2_CLK_PLL1_8, "pll1_8", "pll1_4", 1, 2, 0}, 122 {MMP2_CLK_PLL1_16, "pll1_16", "pll1_8", 1, 2, 0}, 123 {MMP2_CLK_PLL1_20, "pll1_20", "pll1_4", 1, 5, 0}, 124 {MMP2_CLK_PLL1_3, "pll1_3", "pll1", 1, 3, 0}, 125 {MMP2_CLK_PLL1_6, "pll1_6", "pll1_3", 1, 2, 0}, 126 {MMP2_CLK_PLL1_12, "pll1_12", "pll1_6", 1, 2, 0}, 127 {MMP2_CLK_PLL2_2, "pll2_2", "pll2", 1, 2, 0}, 128 {MMP2_CLK_PLL2_4, "pll2_4", "pll2_2", 1, 2, 0}, 129 {MMP2_CLK_PLL2_8, "pll2_8", "pll2_4", 1, 2, 0}, 130 {MMP2_CLK_PLL2_16, "pll2_16", "pll2_8", 1, 2, 0}, 131 {MMP2_CLK_PLL2_3, "pll2_3", "pll2", 1, 3, 0}, 132 {MMP2_CLK_PLL2_6, "pll2_6", "pll2_3", 1, 2, 0}, 133 {MMP2_CLK_PLL2_12, "pll2_12", "pll2_6", 1, 2, 0}, 134 {MMP2_CLK_VCTCXO_2, "vctcxo_2", "vctcxo", 1, 2, 0}, 135 {MMP2_CLK_VCTCXO_4, "vctcxo_4", "vctcxo_2", 1, 2, 0}, 136}; 137 138static struct mmp_clk_factor_masks uart_factor_masks = { 139 .factor = 2, 140 .num_mask = 0x1fff, 141 .den_mask = 0x1fff, 142 .num_shift = 16, 143 .den_shift = 0, 144}; 145 146static struct mmp_clk_factor_tbl uart_factor_tbl[] = { 147 {.num = 8125, .den = 1536}, /*14.745MHZ */ 148 {.num = 3521, .den = 689}, /*19.23MHZ */ 149}; 150 151static struct mmp_clk_factor_masks i2s_factor_masks = { 152 .factor = 2, 153 .num_mask = 0x7fff, 154 .den_mask = 0x1fff, 155 .num_shift = 0, 156 .den_shift = 15, 157 .enable_mask = 0xd0000000, 158}; 159 160static struct mmp_clk_factor_tbl i2s_factor_tbl[] = { 161 {.num = 24868, .den = 511}, /* 2.0480 MHz */ 162 {.num = 28003, .den = 793}, /* 2.8224 MHz */ 163 {.num = 24941, .den = 1025}, /* 4.0960 MHz */ 164 {.num = 28003, .den = 1586}, /* 5.6448 MHz */ 165 {.num = 31158, .den = 2561}, /* 8.1920 MHz */ 166 {.num = 16288, .den = 1845}, /* 11.2896 MHz */ 167 {.num = 20772, .den = 2561}, /* 12.2880 MHz */ 168 {.num = 8144, .den = 1845}, /* 22.5792 MHz */ 169 {.num = 10386, .den = 2561}, /* 24.5760 MHz */ 170}; 171 172static DEFINE_SPINLOCK(acgr_lock); 173 174static struct mmp_param_gate_clk mpmu_gate_clks[] = { 175 {MMP2_CLK_I2S0, "i2s0_clk", "i2s0_pll", CLK_SET_RATE_PARENT, MPMU_ACGR, 0x200000, 0x200000, 0x0, 0, &acgr_lock}, 176 {MMP2_CLK_I2S1, "i2s1_clk", "i2s1_pll", CLK_SET_RATE_PARENT, MPMU_ACGR, 0x100000, 0x100000, 0x0, 0, &acgr_lock}, 177}; 178 179static void mmp2_main_clk_init(struct mmp2_clk_unit *pxa_unit) 180{ 181 struct clk *clk; 182 struct mmp_clk_unit *unit = &pxa_unit->unit; 183 184 mmp_register_fixed_rate_clks(unit, fixed_rate_clks, 185 ARRAY_SIZE(fixed_rate_clks)); 186 187 if (pxa_unit->model == CLK_MODEL_MMP3) { 188 mmp_register_pll_clks(unit, mmp3_pll_clks, 189 pxa_unit->mpmu_base, 190 ARRAY_SIZE(mmp3_pll_clks)); 191 } else { 192 mmp_register_pll_clks(unit, pll_clks, 193 pxa_unit->mpmu_base, 194 ARRAY_SIZE(pll_clks)); 195 } 196 197 mmp_register_fixed_factor_clks(unit, fixed_factor_clks, 198 ARRAY_SIZE(fixed_factor_clks)); 199 200 clk = mmp_clk_register_factor("uart_pll", "pll1_4", 201 CLK_SET_RATE_PARENT, 202 pxa_unit->mpmu_base + MPMU_UART_PLL, 203 &uart_factor_masks, uart_factor_tbl, 204 ARRAY_SIZE(uart_factor_tbl), NULL); 205 mmp_clk_add(unit, MMP2_CLK_UART_PLL, clk); 206 207 mmp_clk_register_factor("i2s0_pll", "pll1_4", 208 CLK_SET_RATE_PARENT, 209 pxa_unit->mpmu_base + MPMU_I2S0_PLL, 210 &i2s_factor_masks, i2s_factor_tbl, 211 ARRAY_SIZE(i2s_factor_tbl), NULL); 212 mmp_clk_register_factor("i2s1_pll", "pll1_4", 213 CLK_SET_RATE_PARENT, 214 pxa_unit->mpmu_base + MPMU_I2S1_PLL, 215 &i2s_factor_masks, i2s_factor_tbl, 216 ARRAY_SIZE(i2s_factor_tbl), NULL); 217 218 mmp_register_gate_clks(unit, mpmu_gate_clks, pxa_unit->mpmu_base, 219 ARRAY_SIZE(mpmu_gate_clks)); 220} 221 222static DEFINE_SPINLOCK(uart0_lock); 223static DEFINE_SPINLOCK(uart1_lock); 224static DEFINE_SPINLOCK(uart2_lock); 225static const char * const uart_parent_names[] = {"uart_pll", "vctcxo"}; 226 227static DEFINE_SPINLOCK(ssp0_lock); 228static DEFINE_SPINLOCK(ssp1_lock); 229static DEFINE_SPINLOCK(ssp2_lock); 230static DEFINE_SPINLOCK(ssp3_lock); 231static const char * const ssp_parent_names[] = {"vctcxo_4", "vctcxo_2", "vctcxo", "pll1_16"}; 232 233static DEFINE_SPINLOCK(timer_lock); 234static const char * const timer_parent_names[] = {"clk32", "vctcxo_4", "vctcxo_2", "vctcxo"}; 235 236static DEFINE_SPINLOCK(reset_lock); 237 238static struct mmp_param_mux_clk apbc_mux_clks[] = { 239 {0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART0, 4, 3, 0, &uart0_lock}, 240 {0, "uart1_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART1, 4, 3, 0, &uart1_lock}, 241 {0, "uart2_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART2, 4, 3, 0, &uart2_lock}, 242 {0, "uart3_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART3, 4, 3, 0, &uart2_lock}, 243 {0, "ssp0_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP0, 4, 3, 0, &ssp0_lock}, 244 {0, "ssp1_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP1, 4, 3, 0, &ssp1_lock}, 245 {0, "ssp2_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP2, 4, 3, 0, &ssp2_lock}, 246 {0, "ssp3_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP3, 4, 3, 0, &ssp3_lock}, 247 {0, "timer_mux", timer_parent_names, ARRAY_SIZE(timer_parent_names), CLK_SET_RATE_PARENT, APBC_TIMER, 4, 3, 0, &timer_lock}, 248}; 249 250static struct mmp_param_gate_clk apbc_gate_clks[] = { 251 {MMP2_CLK_TWSI0, "twsi0_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_TWSI0, 0x7, 0x3, 0x0, 0, &reset_lock}, 252 {MMP2_CLK_TWSI1, "twsi1_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_TWSI1, 0x7, 0x3, 0x0, 0, &reset_lock}, 253 {MMP2_CLK_TWSI2, "twsi2_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_TWSI2, 0x7, 0x3, 0x0, 0, &reset_lock}, 254 {MMP2_CLK_TWSI3, "twsi3_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_TWSI3, 0x7, 0x3, 0x0, 0, &reset_lock}, 255 {MMP2_CLK_TWSI4, "twsi4_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_TWSI4, 0x7, 0x3, 0x0, 0, &reset_lock}, 256 {MMP2_CLK_TWSI5, "twsi5_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_TWSI5, 0x7, 0x3, 0x0, 0, &reset_lock}, 257 {MMP2_CLK_GPIO, "gpio_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_GPIO, 0x7, 0x3, 0x0, 0, &reset_lock}, 258 {MMP2_CLK_KPC, "kpc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_KPC, 0x7, 0x3, 0x0, MMP_CLK_GATE_NEED_DELAY, &reset_lock}, 259 {MMP2_CLK_RTC, "rtc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_RTC, 0x87, 0x83, 0x0, MMP_CLK_GATE_NEED_DELAY, &reset_lock}, 260 {MMP2_CLK_PWM0, "pwm0_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM0, 0x7, 0x3, 0x0, 0, &reset_lock}, 261 {MMP2_CLK_PWM1, "pwm1_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM1, 0x7, 0x3, 0x0, 0, &reset_lock}, 262 {MMP2_CLK_PWM2, "pwm2_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM2, 0x7, 0x3, 0x0, 0, &reset_lock}, 263 {MMP2_CLK_PWM3, "pwm3_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM3, 0x7, 0x3, 0x0, 0, &reset_lock}, 264 /* The gate clocks has mux parent. */ 265 {MMP2_CLK_UART0, "uart0_clk", "uart0_mux", CLK_SET_RATE_PARENT, APBC_UART0, 0x7, 0x3, 0x0, 0, &uart0_lock}, 266 {MMP2_CLK_UART1, "uart1_clk", "uart1_mux", CLK_SET_RATE_PARENT, APBC_UART1, 0x7, 0x3, 0x0, 0, &uart1_lock}, 267 {MMP2_CLK_UART2, "uart2_clk", "uart2_mux", CLK_SET_RATE_PARENT, APBC_UART2, 0x7, 0x3, 0x0, 0, &uart2_lock}, 268 {MMP2_CLK_UART3, "uart3_clk", "uart3_mux", CLK_SET_RATE_PARENT, APBC_UART3, 0x7, 0x3, 0x0, 0, &uart2_lock}, 269 {MMP2_CLK_SSP0, "ssp0_clk", "ssp0_mux", CLK_SET_RATE_PARENT, APBC_SSP0, 0x7, 0x3, 0x0, 0, &ssp0_lock}, 270 {MMP2_CLK_SSP1, "ssp1_clk", "ssp1_mux", CLK_SET_RATE_PARENT, APBC_SSP1, 0x7, 0x3, 0x0, 0, &ssp1_lock}, 271 {MMP2_CLK_SSP2, "ssp2_clk", "ssp2_mux", CLK_SET_RATE_PARENT, APBC_SSP2, 0x7, 0x3, 0x0, 0, &ssp2_lock}, 272 {MMP2_CLK_SSP3, "ssp3_clk", "ssp3_mux", CLK_SET_RATE_PARENT, APBC_SSP3, 0x7, 0x3, 0x0, 0, &ssp3_lock}, 273 {MMP2_CLK_TIMER, "timer_clk", "timer_mux", CLK_SET_RATE_PARENT, APBC_TIMER, 0x7, 0x3, 0x0, 0, &timer_lock}, 274 {MMP2_CLK_THERMAL0, "thermal0_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_THERMAL0, 0x7, 0x3, 0x0, MMP_CLK_GATE_NEED_DELAY, &reset_lock}, 275}; 276 277static struct mmp_param_gate_clk mmp3_apbc_gate_clks[] = { 278 {MMP3_CLK_THERMAL1, "thermal1_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_THERMAL1, 0x7, 0x3, 0x0, MMP_CLK_GATE_NEED_DELAY, &reset_lock}, 279 {MMP3_CLK_THERMAL2, "thermal2_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_THERMAL2, 0x7, 0x3, 0x0, MMP_CLK_GATE_NEED_DELAY, &reset_lock}, 280 {MMP3_CLK_THERMAL3, "thermal3_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_THERMAL3, 0x7, 0x3, 0x0, MMP_CLK_GATE_NEED_DELAY, &reset_lock}, 281}; 282 283static void mmp2_apb_periph_clk_init(struct mmp2_clk_unit *pxa_unit) 284{ 285 struct mmp_clk_unit *unit = &pxa_unit->unit; 286 287 mmp_register_mux_clks(unit, apbc_mux_clks, pxa_unit->apbc_base, 288 ARRAY_SIZE(apbc_mux_clks)); 289 290 mmp_register_gate_clks(unit, apbc_gate_clks, pxa_unit->apbc_base, 291 ARRAY_SIZE(apbc_gate_clks)); 292 293 if (pxa_unit->model == CLK_MODEL_MMP3) { 294 mmp_register_gate_clks(unit, mmp3_apbc_gate_clks, pxa_unit->apbc_base, 295 ARRAY_SIZE(mmp3_apbc_gate_clks)); 296 } 297} 298 299static DEFINE_SPINLOCK(sdh_lock); 300static const char * const sdh_parent_names[] = {"pll1_4", "pll2", "usb_pll", "pll1"}; 301static struct mmp_clk_mix_config sdh_mix_config = { 302 .reg_info = DEFINE_MIX_REG_INFO(4, 10, 2, 8, 32), 303}; 304 305static DEFINE_SPINLOCK(usb_lock); 306static DEFINE_SPINLOCK(usbhsic0_lock); 307static DEFINE_SPINLOCK(usbhsic1_lock); 308 309static DEFINE_SPINLOCK(disp0_lock); 310static DEFINE_SPINLOCK(disp1_lock); 311static const char * const disp_parent_names[] = {"pll1", "pll1_16", "pll2", "vctcxo"}; 312 313static DEFINE_SPINLOCK(ccic0_lock); 314static DEFINE_SPINLOCK(ccic1_lock); 315static const char * const ccic_parent_names[] = {"pll1_2", "pll1_16", "vctcxo"}; 316 317static DEFINE_SPINLOCK(gpu_lock); 318static const char * const mmp2_gpu_gc_parent_names[] = {"pll1_2", "pll1_3", "pll2_2", "pll2_3", "pll2", "usb_pll"}; 319static const u32 mmp2_gpu_gc_parent_table[] = { 0x0000, 0x0040, 0x0080, 0x00c0, 0x1000, 0x1040 }; 320static const char * const mmp2_gpu_bus_parent_names[] = {"pll1_4", "pll2", "pll2_2", "usb_pll"}; 321static const u32 mmp2_gpu_bus_parent_table[] = { 0x0000, 0x0020, 0x0030, 0x4020 }; 322static const char * const mmp3_gpu_bus_parent_names[] = {"pll1_4", "pll1_6", "pll1_2", "pll2_2"}; 323static const char * const mmp3_gpu_gc_parent_names[] = {"pll1", "pll2", "pll1_p", "pll2_p"}; 324 325static DEFINE_SPINLOCK(audio_lock); 326 327static struct mmp_clk_mix_config ccic0_mix_config = { 328 .reg_info = DEFINE_MIX_REG_INFO(4, 17, 2, 6, 32), 329}; 330static struct mmp_clk_mix_config ccic1_mix_config = { 331 .reg_info = DEFINE_MIX_REG_INFO(4, 16, 2, 6, 32), 332}; 333 334static struct mmp_param_mux_clk apmu_mux_clks[] = { 335 {MMP2_CLK_DISP0_MUX, "disp0_mux", disp_parent_names, ARRAY_SIZE(disp_parent_names), CLK_SET_RATE_PARENT, APMU_DISP0, 6, 2, 0, &disp0_lock}, 336 {MMP2_CLK_DISP1_MUX, "disp1_mux", disp_parent_names, ARRAY_SIZE(disp_parent_names), CLK_SET_RATE_PARENT, APMU_DISP1, 6, 2, 0, &disp1_lock}, 337}; 338 339static struct mmp_param_mux_clk mmp3_apmu_mux_clks[] = { 340 {0, "gpu_bus_mux", mmp3_gpu_bus_parent_names, ARRAY_SIZE(mmp3_gpu_bus_parent_names), 341 CLK_SET_RATE_PARENT, APMU_GPU, 4, 2, 0, &gpu_lock}, 342 {0, "gpu_3d_mux", mmp3_gpu_gc_parent_names, ARRAY_SIZE(mmp3_gpu_gc_parent_names), 343 CLK_SET_RATE_PARENT, APMU_GPU, 6, 2, 0, &gpu_lock}, 344 {0, "gpu_2d_mux", mmp3_gpu_gc_parent_names, ARRAY_SIZE(mmp3_gpu_gc_parent_names), 345 CLK_SET_RATE_PARENT, APMU_GPU, 12, 2, 0, &gpu_lock}, 346}; 347 348static struct mmp_param_div_clk apmu_div_clks[] = { 349 {0, "disp0_div", "disp0_mux", CLK_SET_RATE_PARENT, APMU_DISP0, 8, 4, CLK_DIVIDER_ONE_BASED, &disp0_lock}, 350 {0, "disp0_sphy_div", "disp0_mux", CLK_SET_RATE_PARENT, APMU_DISP0, 15, 5, 0, &disp0_lock}, 351 {0, "disp1_div", "disp1_mux", CLK_SET_RATE_PARENT, APMU_DISP1, 8, 4, CLK_DIVIDER_ONE_BASED, &disp1_lock}, 352 {0, "ccic0_sphy_div", "ccic0_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC0, 10, 5, 0, &ccic0_lock}, 353 {0, "ccic1_sphy_div", "ccic1_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC1, 10, 5, 0, &ccic1_lock}, 354}; 355 356static struct mmp_param_div_clk mmp3_apmu_div_clks[] = { 357 {0, "gpu_3d_div", "gpu_3d_mux", CLK_SET_RATE_PARENT, APMU_GPU, 24, 4, 0, &gpu_lock}, 358 {0, "gpu_2d_div", "gpu_2d_mux", CLK_SET_RATE_PARENT, APMU_GPU, 28, 4, 0, &gpu_lock}, 359}; 360 361static struct mmp_param_gate_clk apmu_gate_clks[] = { 362 {MMP2_CLK_USB, "usb_clk", "usb_pll", 0, APMU_USB, 0x9, 0x9, 0x0, 0, &usb_lock}, 363 {MMP2_CLK_USBHSIC0, "usbhsic0_clk", "usb_pll", 0, APMU_USBHSIC0, 0x1b, 0x1b, 0x0, 0, &usbhsic0_lock}, 364 {MMP2_CLK_USBHSIC1, "usbhsic1_clk", "usb_pll", 0, APMU_USBHSIC1, 0x1b, 0x1b, 0x0, 0, &usbhsic1_lock}, 365 /* The gate clocks has mux parent. */ 366 {MMP2_CLK_SDH0, "sdh0_clk", "sdh_mix_clk", CLK_SET_RATE_PARENT, APMU_SDH0, 0x1b, 0x1b, 0x0, 0, &sdh_lock}, 367 {MMP2_CLK_SDH1, "sdh1_clk", "sdh_mix_clk", CLK_SET_RATE_PARENT, APMU_SDH1, 0x1b, 0x1b, 0x0, 0, &sdh_lock}, 368 {MMP2_CLK_SDH2, "sdh2_clk", "sdh_mix_clk", CLK_SET_RATE_PARENT, APMU_SDH2, 0x1b, 0x1b, 0x0, 0, &sdh_lock}, 369 {MMP2_CLK_SDH3, "sdh3_clk", "sdh_mix_clk", CLK_SET_RATE_PARENT, APMU_SDH3, 0x1b, 0x1b, 0x0, 0, &sdh_lock}, 370 {MMP2_CLK_DISP0, "disp0_clk", "disp0_div", CLK_SET_RATE_PARENT, APMU_DISP0, 0x12, 0x12, 0x0, 0, &disp0_lock}, 371 {MMP2_CLK_DISP0_LCDC, "disp0_lcdc_clk", "disp0_mux", CLK_SET_RATE_PARENT, APMU_DISP0, 0x09, 0x09, 0x0, 0, &disp0_lock}, 372 {MMP2_CLK_DISP0_SPHY, "disp0_sphy_clk", "disp0_sphy_div", CLK_SET_RATE_PARENT, APMU_DISP0, 0x1024, 0x1024, 0x0, 0, &disp0_lock}, 373 {MMP2_CLK_DISP1, "disp1_clk", "disp1_div", CLK_SET_RATE_PARENT, APMU_DISP1, 0x09, 0x09, 0x0, 0, &disp1_lock}, 374 {MMP2_CLK_CCIC_ARBITER, "ccic_arbiter", "vctcxo", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x1800, 0x1800, 0x0, 0, &ccic0_lock}, 375 {MMP2_CLK_CCIC0, "ccic0_clk", "ccic0_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x1b, 0x1b, 0x0, 0, &ccic0_lock}, 376 {MMP2_CLK_CCIC0_PHY, "ccic0_phy_clk", "ccic0_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x24, 0x24, 0x0, 0, &ccic0_lock}, 377 {MMP2_CLK_CCIC0_SPHY, "ccic0_sphy_clk", "ccic0_sphy_div", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x300, 0x300, 0x0, 0, &ccic0_lock}, 378 {MMP2_CLK_CCIC1, "ccic1_clk", "ccic1_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC1, 0x1b, 0x1b, 0x0, 0, &ccic1_lock}, 379 {MMP2_CLK_CCIC1_PHY, "ccic1_phy_clk", "ccic1_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC1, 0x24, 0x24, 0x0, 0, &ccic1_lock}, 380 {MMP2_CLK_CCIC1_SPHY, "ccic1_sphy_clk", "ccic1_sphy_div", CLK_SET_RATE_PARENT, APMU_CCIC1, 0x300, 0x300, 0x0, 0, &ccic1_lock}, 381 {MMP2_CLK_GPU_BUS, "gpu_bus_clk", "gpu_bus_mux", CLK_SET_RATE_PARENT, APMU_GPU, 0xa, 0xa, 0x0, MMP_CLK_GATE_NEED_DELAY, &gpu_lock}, 382 {MMP2_CLK_AUDIO, "audio_clk", "audio_mix_clk", CLK_SET_RATE_PARENT, APMU_AUDIO, 0x12, 0x12, 0x0, 0, &audio_lock}, 383}; 384 385static struct mmp_param_gate_clk mmp2_apmu_gate_clks[] = { 386 {MMP2_CLK_GPU_3D, "gpu_3d_clk", "gpu_3d_mux", CLK_SET_RATE_PARENT, APMU_GPU, 0x5, 0x5, 0x0, MMP_CLK_GATE_NEED_DELAY, &gpu_lock}, 387}; 388 389static struct mmp_param_gate_clk mmp3_apmu_gate_clks[] = { 390 {MMP3_CLK_SDH4, "sdh4_clk", "sdh_mix_clk", CLK_SET_RATE_PARENT, APMU_SDH4, 0x1b, 0x1b, 0x0, 0, &sdh_lock}, 391 {MMP3_CLK_GPU_3D, "gpu_3d_clk", "gpu_3d_div", CLK_SET_RATE_PARENT, APMU_GPU, 0x5, 0x5, 0x0, MMP_CLK_GATE_NEED_DELAY, &gpu_lock}, 392 {MMP3_CLK_GPU_2D, "gpu_2d_clk", "gpu_2d_div", CLK_SET_RATE_PARENT, APMU_GPU, 0x1c0000, 0x1c0000, 0x0, MMP_CLK_GATE_NEED_DELAY, &gpu_lock}, 393}; 394 395static void mmp2_axi_periph_clk_init(struct mmp2_clk_unit *pxa_unit) 396{ 397 struct clk *clk; 398 struct mmp_clk_unit *unit = &pxa_unit->unit; 399 400 sdh_mix_config.reg_info.reg_clk_ctrl = pxa_unit->apmu_base + APMU_SDH0; 401 clk = mmp_clk_register_mix(NULL, "sdh_mix_clk", sdh_parent_names, 402 ARRAY_SIZE(sdh_parent_names), 403 CLK_SET_RATE_PARENT, 404 &sdh_mix_config, &sdh_lock); 405 406 ccic0_mix_config.reg_info.reg_clk_ctrl = pxa_unit->apmu_base + APMU_CCIC0; 407 clk = mmp_clk_register_mix(NULL, "ccic0_mix_clk", ccic_parent_names, 408 ARRAY_SIZE(ccic_parent_names), 409 CLK_SET_RATE_PARENT, 410 &ccic0_mix_config, &ccic0_lock); 411 mmp_clk_add(unit, MMP2_CLK_CCIC0_MIX, clk); 412 413 ccic1_mix_config.reg_info.reg_clk_ctrl = pxa_unit->apmu_base + APMU_CCIC1; 414 clk = mmp_clk_register_mix(NULL, "ccic1_mix_clk", ccic_parent_names, 415 ARRAY_SIZE(ccic_parent_names), 416 CLK_SET_RATE_PARENT, 417 &ccic1_mix_config, &ccic1_lock); 418 mmp_clk_add(unit, MMP2_CLK_CCIC1_MIX, clk); 419 420 mmp_register_mux_clks(unit, apmu_mux_clks, pxa_unit->apmu_base, 421 ARRAY_SIZE(apmu_mux_clks)); 422 423 mmp_register_div_clks(unit, apmu_div_clks, pxa_unit->apmu_base, 424 ARRAY_SIZE(apmu_div_clks)); 425 426 mmp_register_gate_clks(unit, apmu_gate_clks, pxa_unit->apmu_base, 427 ARRAY_SIZE(apmu_gate_clks)); 428 429 if (pxa_unit->model == CLK_MODEL_MMP3) { 430 mmp_register_mux_clks(unit, mmp3_apmu_mux_clks, pxa_unit->apmu_base, 431 ARRAY_SIZE(mmp3_apmu_mux_clks)); 432 433 mmp_register_div_clks(unit, mmp3_apmu_div_clks, pxa_unit->apmu_base, 434 ARRAY_SIZE(mmp3_apmu_div_clks)); 435 436 mmp_register_gate_clks(unit, mmp3_apmu_gate_clks, pxa_unit->apmu_base, 437 ARRAY_SIZE(mmp3_apmu_gate_clks)); 438 } else { 439 clk_register_mux_table(NULL, "gpu_3d_mux", mmp2_gpu_gc_parent_names, 440 ARRAY_SIZE(mmp2_gpu_gc_parent_names), 441 CLK_SET_RATE_PARENT, 442 pxa_unit->apmu_base + APMU_GPU, 443 0, 0x10c0, 0, 444 mmp2_gpu_gc_parent_table, &gpu_lock); 445 446 clk_register_mux_table(NULL, "gpu_bus_mux", mmp2_gpu_bus_parent_names, 447 ARRAY_SIZE(mmp2_gpu_bus_parent_names), 448 CLK_SET_RATE_PARENT, 449 pxa_unit->apmu_base + APMU_GPU, 450 0, 0x4030, 0, 451 mmp2_gpu_bus_parent_table, &gpu_lock); 452 453 mmp_register_gate_clks(unit, mmp2_apmu_gate_clks, pxa_unit->apmu_base, 454 ARRAY_SIZE(mmp2_apmu_gate_clks)); 455 } 456} 457 458static void mmp2_clk_reset_init(struct device_node *np, 459 struct mmp2_clk_unit *pxa_unit) 460{ 461 struct mmp_clk_reset_cell *cells; 462 int i, nr_resets; 463 464 nr_resets = ARRAY_SIZE(apbc_gate_clks); 465 cells = kcalloc(nr_resets, sizeof(*cells), GFP_KERNEL); 466 if (!cells) 467 return; 468 469 for (i = 0; i < nr_resets; i++) { 470 cells[i].clk_id = apbc_gate_clks[i].id; 471 cells[i].reg = pxa_unit->apbc_base + apbc_gate_clks[i].offset; 472 cells[i].flags = 0; 473 cells[i].lock = apbc_gate_clks[i].lock; 474 cells[i].bits = 0x4; 475 } 476 477 mmp_clk_reset_register(np, cells, nr_resets); 478} 479 480static void mmp2_pm_domain_init(struct device_node *np, 481 struct mmp2_clk_unit *pxa_unit) 482{ 483 if (pxa_unit->model == CLK_MODEL_MMP3) { 484 pxa_unit->pm_domains[MMP2_POWER_DOMAIN_GPU] 485 = mmp_pm_domain_register("gpu", 486 pxa_unit->apmu_base + APMU_GPU, 487 0x0600, 0x40003, 0x18000c, 0, &gpu_lock); 488 } else { 489 pxa_unit->pm_domains[MMP2_POWER_DOMAIN_GPU] 490 = mmp_pm_domain_register("gpu", 491 pxa_unit->apmu_base + APMU_GPU, 492 0x8600, 0x00003, 0x00000c, 493 MMP_PM_DOMAIN_NO_DISABLE, &gpu_lock); 494 } 495 pxa_unit->pd_data.num_domains++; 496 497 pxa_unit->pm_domains[MMP2_POWER_DOMAIN_AUDIO] 498 = mmp_pm_domain_register("audio", 499 pxa_unit->apmu_base + APMU_AUDIO, 500 0x600, 0x2, 0, 0, &audio_lock); 501 pxa_unit->pd_data.num_domains++; 502 503 if (pxa_unit->model == CLK_MODEL_MMP3) { 504 pxa_unit->pm_domains[MMP3_POWER_DOMAIN_CAMERA] 505 = mmp_pm_domain_register("camera", 506 pxa_unit->apmu_base + APMU_CAMERA, 507 0x600, 0, 0, 0, NULL); 508 pxa_unit->pd_data.num_domains++; 509 } 510 511 pxa_unit->pd_data.domains = pxa_unit->pm_domains; 512 of_genpd_add_provider_onecell(np, &pxa_unit->pd_data); 513} 514 515static void __init mmp2_clk_init(struct device_node *np) 516{ 517 struct mmp2_clk_unit *pxa_unit; 518 519 pxa_unit = kzalloc(sizeof(*pxa_unit), GFP_KERNEL); 520 if (!pxa_unit) 521 return; 522 523 if (of_device_is_compatible(np, "marvell,mmp3-clock")) 524 pxa_unit->model = CLK_MODEL_MMP3; 525 else 526 pxa_unit->model = CLK_MODEL_MMP2; 527 528 pxa_unit->mpmu_base = of_iomap(np, 0); 529 if (!pxa_unit->mpmu_base) { 530 pr_err("failed to map mpmu registers\n"); 531 goto free_memory; 532 } 533 534 pxa_unit->apmu_base = of_iomap(np, 1); 535 if (!pxa_unit->apmu_base) { 536 pr_err("failed to map apmu registers\n"); 537 goto unmap_mpmu_region; 538 } 539 540 pxa_unit->apbc_base = of_iomap(np, 2); 541 if (!pxa_unit->apbc_base) { 542 pr_err("failed to map apbc registers\n"); 543 goto unmap_apmu_region; 544 } 545 546 mmp2_pm_domain_init(np, pxa_unit); 547 548 mmp_clk_init(np, &pxa_unit->unit, NR_CLKS); 549 550 mmp2_main_clk_init(pxa_unit); 551 552 mmp2_apb_periph_clk_init(pxa_unit); 553 554 mmp2_axi_periph_clk_init(pxa_unit); 555 556 mmp2_clk_reset_init(np, pxa_unit); 557 558 return; 559 560unmap_apmu_region: 561 iounmap(pxa_unit->apmu_base); 562unmap_mpmu_region: 563 iounmap(pxa_unit->mpmu_base); 564free_memory: 565 kfree(pxa_unit); 566} 567 568CLK_OF_DECLARE(mmp2_clk, "marvell,mmp2-clock", mmp2_clk_init); 569CLK_OF_DECLARE(mmp3_clk, "marvell,mmp3-clock", mmp2_clk_init); 570