Searched refs:reg_offset (Results 1 - 25 of 374) sorted by relevance

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/linux-master/drivers/mfd/
H A Dsec-irq.c21 .reg_offset = 0,
25 .reg_offset = 0,
29 .reg_offset = 0,
33 .reg_offset = 0,
37 .reg_offset = 0,
41 .reg_offset = 0,
45 .reg_offset = 0,
49 .reg_offset = 0,
53 .reg_offset = 1,
57 .reg_offset
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H A Dda9052-irq.c37 .reg_offset = 0,
41 .reg_offset = 0,
45 .reg_offset = 0,
49 .reg_offset = 0,
53 .reg_offset = 0,
57 .reg_offset = 0,
61 .reg_offset = 0,
65 .reg_offset = 0,
69 .reg_offset = 1,
73 .reg_offset
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H A Dmax8907.c115 { .reg_offset = 0, .mask = 1 << 0, },
116 { .reg_offset = 0, .mask = 1 << 1, },
117 { .reg_offset = 0, .mask = 1 << 2, },
118 { .reg_offset = 1, .mask = 1 << 0, },
119 { .reg_offset = 1, .mask = 1 << 1, },
120 { .reg_offset = 1, .mask = 1 << 2, },
121 { .reg_offset = 1, .mask = 1 << 3, },
122 { .reg_offset = 1, .mask = 1 << 4, },
123 { .reg_offset = 1, .mask = 1 << 5, },
124 { .reg_offset
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H A Dpalmas.c74 .reg_offset = 1,
78 .reg_offset = 1,
82 .reg_offset = 1,
86 .reg_offset = 1,
90 .reg_offset = 1,
94 .reg_offset = 1,
98 .reg_offset = 1,
102 .reg_offset = 1,
107 .reg_offset = 2,
111 .reg_offset
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H A Dtps65910.c54 .reg_offset = 0,
58 .reg_offset = 0,
62 .reg_offset = 0,
66 .reg_offset = 0,
70 .reg_offset = 0,
74 .reg_offset = 0,
78 .reg_offset = 0,
82 .reg_offset = 0,
88 .reg_offset = 1,
92 .reg_offset
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H A Das3722.c89 .reg_offset = 1,
93 .reg_offset = 1,
97 .reg_offset = 1,
101 .reg_offset = 1,
105 .reg_offset = 1,
109 .reg_offset = 1,
113 .reg_offset = 1,
117 .reg_offset = 1,
123 .reg_offset = 2,
127 .reg_offset
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H A Dwm8994-irq.c28 .reg_offset = 1,
32 .reg_offset = 1,
36 .reg_offset = 1,
40 .reg_offset = 1,
44 .reg_offset = 1,
48 .reg_offset = 1,
52 .reg_offset = 1,
56 .reg_offset = 1,
60 .reg_offset = 1,
64 .reg_offset
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H A Dmax14577.c194 { .reg_offset = 0, .mask = MAX14577_INT1_ADC_MASK, },
195 { .reg_offset = 0, .mask = MAX14577_INT1_ADCLOW_MASK, },
196 { .reg_offset = 0, .mask = MAX14577_INT1_ADCERR_MASK, },
198 { .reg_offset = 1, .mask = MAX14577_INT2_CHGTYP_MASK, },
199 { .reg_offset = 1, .mask = MAX14577_INT2_CHGDETRUN_MASK, },
200 { .reg_offset = 1, .mask = MAX14577_INT2_DCDTMR_MASK, },
201 { .reg_offset = 1, .mask = MAX14577_INT2_DBCHG_MASK, },
202 { .reg_offset = 1, .mask = MAX14577_INT2_VBVOLT_MASK, },
204 { .reg_offset = 2, .mask = MAX14577_INT3_EOC_MASK, },
205 { .reg_offset
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/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Daldebaran_reg_init.c34 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
35 adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i]));
36 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i]));
37 adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i]));
38 adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));
39 adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i]));
40 adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i]));
41 adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i]));
42 adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i]));
43 adev->reg_offset[SDMA0_HWI
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H A Ddimgrey_cavefish_reg_init.c35 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
36 adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i]));
37 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i]));
38 adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i]));
39 adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));
40 adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i]));
41 adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i]));
42 adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(VCN0_BASE.instance[i]));
43 adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i]));
44 adev->reg_offset[DCE_HWI
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H A Darct_reg_init.c34 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
35 adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i]));
36 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i]));
37 adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i]));
38 adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIF0_BASE.instance[i]));
39 adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i]));
40 adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i]));
41 adev->reg_offset[UVD_HWIP][i] = (uint32_t *)(&(UVD_BASE.instance[i]));
42 adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i]));
43 adev->reg_offset[OSSSYS_HWI
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H A Dvega10_reg_init.c34 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
35 adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i]));
36 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i]));
37 adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i]));
38 adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));
39 adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i]));
40 adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i]));
41 adev->reg_offset[UVD_HWIP][i] = (uint32_t *)(&(UVD_BASE.instance[i]));
42 adev->reg_offset[VCE_HWIP][i] = (uint32_t *)(&(VCE_BASE.instance[i]));
43 adev->reg_offset[VCN_HWI
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H A Dmmsch_v1_0.h61 uint32_t reg_offset : 28; member in struct:mmsch_v1_0_cmd_direct_reg_header
66 uint32_t reg_offset : 20; member in struct:mmsch_v1_0_cmd_indirect_reg_header
99 uint32_t reg_offset,
102 direct_wt->cmd_header.reg_offset = reg_offset;
109 uint32_t reg_offset,
112 direct_rd_mod_wt->cmd_header.reg_offset = reg_offset;
121 uint32_t reg_offset,
124 direct_poll->cmd_header.reg_offset
97 mmsch_v1_0_insert_direct_wt(struct mmsch_v1_0_cmd_direct_write *direct_wt, uint32_t *init_table, uint32_t reg_offset, uint32_t value) argument
107 mmsch_v1_0_insert_direct_rd_mod_wt(struct mmsch_v1_0_cmd_direct_read_modify_write *direct_rd_mod_wt, uint32_t *init_table, uint32_t reg_offset, uint32_t mask, uint32_t data) argument
119 mmsch_v1_0_insert_direct_poll(struct mmsch_v1_0_cmd_direct_polling *direct_poll, uint32_t *init_table, uint32_t reg_offset, uint32_t mask, uint32_t wait) argument
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H A Dvega20_reg_init.c34 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
35 adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i]));
36 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i]));
37 adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i]));
38 adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));
39 adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i]));
40 adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i]));
41 adev->reg_offset[UVD_HWIP][i] = (uint32_t *)(&(UVD_BASE.instance[i]));
42 adev->reg_offset[VCE_HWIP][i] = (uint32_t *)(&(VCE_BASE.instance[i]));
43 adev->reg_offset[DF_HWI
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H A Dsoc15_common.h36 #define SOC15_REG_OFFSET(ip, inst, reg) (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)
38 (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + (reg)+(offset))
51 __WREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \
53 adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \
59 __WREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][idx][reg##reg_name##_BASE_IDX] + reg##reg_name, \
61 adev->reg_offset[ip##_HWIP][idx][reg##reg_name##_BASE_IDX] + reg##reg_name, \
67 __RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \
75 __RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \
79 __RREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + (reg)) + \
83 __WREG32_SOC15_RLC__((adev->reg_offset[i
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H A Djpeg_v1_0.c38 static void jpeg_v1_0_decode_ring_patch_wreg(struct amdgpu_ring *ring, uint32_t *ptr, uint32_t reg_offset, uint32_t val) argument
42 if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) ||
43 ((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) {
45 ring->ring[(*ptr)++] = PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0);
47 ring->ring[(*ptr)++] = reg_offset;
57 uint32_t reg, reg_offset, val, mask, i; local
61 reg_offset = (reg << 2);
63 jpeg_v1_0_decode_ring_patch_wreg(ring, &ptr, reg_offset, va
351 uint32_t reg_offset = (reg << 2); local
395 uint32_t reg_offset = (reg << 2); local
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H A Dmmsch_v3_0.h56 uint32_t reg_offset : 28; member in struct:mmsch_v3_0_cmd_direct_reg_header
61 uint32_t reg_offset : 20; member in struct:mmsch_v3_0_cmd_indirect_reg_header
95 direct_rd_mod_wt.cmd_header.reg_offset = reg; \
106 direct_wt.cmd_header.reg_offset = reg; \
116 direct_poll.cmd_header.reg_offset = reg; \
/linux-master/drivers/gpu/drm/loongson/
H A Dloongson_device.c43 .reg_offset = LS7A1000_PLL_GFX_REG,
48 .reg_offset = LS7A1000_PIXPLL0_REG,
52 .reg_offset = LS7A1000_PIXPLL1_REG,
75 .reg_offset = LS7A2000_PLL_GFX_REG,
80 .reg_offset = LS7A2000_PIXPLL0_REG,
84 .reg_offset = LS7A2000_PIXPLL1_REG,
/linux-master/arch/powerpc/boot/
H A Dns16550.c60 u32 reg_offset; local
67 n = getprop(devp, "reg-offset", &reg_offset, sizeof(reg_offset));
68 if (n == sizeof(reg_offset))
69 reg_base += be32_to_cpu(reg_offset);
/linux-master/drivers/gpio/
H A Dgpio-madera.c28 unsigned int reg_offset = 2 * offset; local
32 ret = regmap_read(madera->regmap, MADERA_GPIO1_CTRL_2 + reg_offset,
47 unsigned int reg_offset = 2 * offset; local
50 MADERA_GPIO1_CTRL_2 + reg_offset,
58 unsigned int reg_offset = 2 * offset; local
62 ret = regmap_read(madera->regmap, MADERA_GPIO1_CTRL_1 + reg_offset,
75 unsigned int reg_offset = 2 * offset; local
80 MADERA_GPIO1_CTRL_2 + reg_offset,
86 MADERA_GPIO1_CTRL_1 + reg_offset,
95 unsigned int reg_offset local
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/linux-master/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dcommon_baco.h38 uint32_t reg_offset; member in struct:baco_cmd_entry
50 uint32_t reg_offset; member in struct:soc15_baco_cmd_entry
/linux-master/drivers/gpu/drm/msm/disp/mdp5/
H A Dmdp5_pipe.h20 uint32_t reg_offset; member in struct:mdp5_hw_pipe
44 uint32_t reg_offset, uint32_t caps);
/linux-master/include/linux/platform_data/
H A Dhsmmc-omap.h46 u16 reg_offset; member in struct:omap_hsmmc_platform_data
/linux-master/sound/soc/sof/amd/
H A Dacp-stream.c41 stream->reg_offset = PTE_GRP1_OFFSET;
47 stream->reg_offset = PTE_GRP2_OFFSET;
53 stream->reg_offset = PTE_GRP3_OFFSET;
59 stream->reg_offset = PTE_GRP4_OFFSET;
65 stream->reg_offset = PTE_GRP5_OFFSET;
71 stream->reg_offset = PTE_GRP6_OFFSET;
77 stream->reg_offset = PTE_GRP7_OFFSET;
83 stream->reg_offset = PTE_GRP8_OFFSET;
93 offsetof(struct scratch_reg_conf, reg_offset);
98 phy_addr_offset, stream->reg_offset);
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/linux-master/drivers/pinctrl/realtek/
H A Dpinctrl-rtd.h29 unsigned int reg_offset; member in struct:rtd_pin_config_desc
41 unsigned int reg_offset; member in struct:rtd_pin_sconfig_desc
58 unsigned int reg_offset; member in struct:rtd_pin_reg_list
78 .reg_offset = _reg_off, \
92 .reg_offset = _reg_off, \

Completed in 348 milliseconds

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