amd/amdgpu/jpeg_v1_0.c

38 static void jpeg_v1_0_decode_ring_patch_wreg(struct amdgpu_ring *ring, uint32_t *ptr, uint32_t reg_offset, uint32_t val)
42 	if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) ||
43 		((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) {
45 		ring->ring[(*ptr)++] = PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0);
47 		ring->ring[(*ptr)++] = reg_offset;
57 	uint32_t reg, reg_offset, val, mask, i;
61 	reg_offset = (reg << 2);
63 	jpeg_v1_0_decode_ring_patch_wreg(ring, &ptr, reg_offset, val);
67 	reg_offset = (reg << 2);
69 	jpeg_v1_0_decode_ring_patch_wreg(ring, &ptr, reg_offset, val);
79 	reg_offset = (reg << 2);
81 	jpeg_v1_0_decode_ring_patch_wreg(ring, &ptr, reg_offset, val);
85 	reg_offset = (reg << 2);
87 	jpeg_v1_0_decode_ring_patch_wreg(ring, &ptr, reg_offset, val);
91 	reg_offset = (reg << 2);
100 	if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) ||
101 		((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) {
103 		ring->ring[ptr++] = PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3);
105 		ring->ring[ptr++] = reg_offset;
118 	reg_offset = (reg << 2);
120 	jpeg_v1_0_decode_ring_patch_wreg(ring, &ptr, reg_offset, val);
124 	reg_offset = (reg << 2);
126 	jpeg_v1_0_decode_ring_patch_wreg(ring, &ptr, reg_offset, val);
351 	uint32_t reg_offset = (reg << 2);
363 	if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) ||
364 		((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) {
367 			PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3));
369 		amdgpu_ring_write(ring, reg_offset);
395 	uint32_t reg_offset = (reg << 2);
399 	if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) ||
400 			((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) {
403 			PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0));
405 		amdgpu_ring_write(ring, reg_offset);