Searched refs:reg_num (Results 1 - 25 of 161) sorted by relevance

1234567

/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn201/
H A Dirq_service_dcn201.c152 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
153 .enable_reg = SRI(reg1, block, reg_num),\
155 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
157 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
158 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
160 .ack_reg = SRI(reg2, block, reg_num),\
162 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
164 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
166 #define hpd_int_entry(reg_num)\
167 [DC_IRQ_SOURCE_HPD1 + reg_num]
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn303/
H A Dirq_service_dcn303.c138 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
139 .enable_reg = SRI(reg1, block, reg_num),\
140 .enable_mask = block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
142 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
143 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
145 .ack_reg = SRI(reg2, block, reg_num),\
146 .ack_mask = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
147 .ack_value = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
151 #define hpd_int_entry(reg_num)\
152 [DC_IRQ_SOURCE_HPD1 + reg_num]
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn10/
H A Dirq_service_dcn10.c200 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
201 .enable_reg = SRI(reg1, block, reg_num),\
203 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
205 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
206 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
208 .ack_reg = SRI(reg2, block, reg_num),\
210 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
212 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
214 #define hpd_int_entry(reg_num)\
215 [DC_IRQ_SOURCE_HPD1 + reg_num]
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn20/
H A Dirq_service_dcn20.c203 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
204 .enable_reg = SRI(reg1, block, reg_num),\
206 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
208 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
209 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
211 .ack_reg = SRI(reg2, block, reg_num),\
213 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
215 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
219 #define hpd_int_entry(reg_num)\
220 [DC_IRQ_SOURCE_HPD1 + reg_num]
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/irq/dce120/
H A Dirq_service_dce120.c103 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
104 .enable_reg = SRI(reg1, block, reg_num),\
106 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
108 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
109 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
111 .ack_reg = SRI(reg2, block, reg_num),\
113 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
115 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
117 #define hpd_int_entry(reg_num)\
118 [DC_IRQ_SOURCE_HPD1 + reg_num]
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn35/
H A Dirq_service_dcn35.c207 #define IRQ_REG_ENTRY(base, block, reg_num, reg1, mask1, reg2, mask2)\
208 REG_STRUCT[base + reg_num].enable_reg = SRI(reg1, block, reg_num),\
209 REG_STRUCT[base + reg_num].enable_mask = \
210 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
211 REG_STRUCT[base + reg_num].enable_value[0] = \
212 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
213 REG_STRUCT[base + reg_num].enable_value[1] = \
214 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK, \
215 REG_STRUCT[base + reg_num]
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn351/
H A Dirq_service_dcn351.c186 #define IRQ_REG_ENTRY(base, block, reg_num, reg1, mask1, reg2, mask2)\
187 REG_STRUCT[base + reg_num].enable_reg = SRI(reg1, block, reg_num),\
188 REG_STRUCT[base + reg_num].enable_mask = \
189 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
190 REG_STRUCT[base + reg_num].enable_value[0] = \
191 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
192 REG_STRUCT[base + reg_num].enable_value[1] = \
193 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK, \
194 REG_STRUCT[base + reg_num]
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/irq/dce110/
H A Dirq_service_dce110.c89 #define hpd_int_entry(reg_num)\
90 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
91 .enable_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\
97 .ack_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\
100 .status_reg = mmHPD ## reg_num ## _DC_HPD_INT_STATUS,\
104 #define hpd_rx_int_entry(reg_num)\
105 [DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
106 .enable_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\
111 .ack_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\
114 .status_reg = mmHPD ## reg_num ## _DC_HPD_INT_STATU
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/irq/dce80/
H A Dirq_service_dce80.c92 #define hpd_int_entry(reg_num)\
93 [DC_IRQ_SOURCE_INVALID + reg_num] = {\
94 .enable_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
100 .ack_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
103 .status_reg = mmDC_HPD ## reg_num ## _INT_STATUS,\
107 #define hpd_rx_int_entry(reg_num)\
108 [DC_IRQ_SOURCE_HPD6 + reg_num] = {\
109 .enable_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
114 .ack_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
117 .status_reg = mmDC_HPD ## reg_num ## _INT_STATU
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/irq/dce60/
H A Dirq_service_dce60.c101 #define hpd_int_entry(reg_num)\
102 [DC_IRQ_SOURCE_INVALID + reg_num] = {\
103 .enable_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
109 .ack_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
112 .status_reg = mmDC_HPD ## reg_num ## _INT_STATUS,\
116 #define hpd_rx_int_entry(reg_num)\
117 [DC_IRQ_SOURCE_HPD6 + reg_num] = {\
118 .enable_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
123 .ack_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
126 .status_reg = mmDC_HPD ## reg_num ## _INT_STATU
[all...]
/linux-master/arch/riscv/kvm/
H A Dvcpu_fp.c84 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | local
93 if (reg_num == KVM_REG_RISCV_FP_F_REG(fcsr))
95 else if ((KVM_REG_RISCV_FP_F_REG(f[0]) <= reg_num) &&
96 reg_num <= KVM_REG_RISCV_FP_F_REG(f[31]))
97 reg_val = &cntx->fp.f.f[reg_num];
102 if (reg_num == KVM_REG_RISCV_FP_D_REG(fcsr)) {
106 } else if ((KVM_REG_RISCV_FP_D_REG(f[0]) <= reg_num) &&
107 reg_num <= KVM_REG_RISCV_FP_D_REG(f[31])) {
110 reg_val = &cntx->fp.d.f[reg_num];
129 unsigned long reg_num local
[all...]
H A Dvcpu_onereg.c188 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | local
196 switch (reg_num) {
237 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | local
248 switch (reg_num) {
342 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | local
349 if (reg_num >= sizeof(struct kvm_riscv_core) / sizeof(unsigned long))
352 if (reg_num == KVM_REG_RISCV_CORE_REG(regs.pc))
354 else if (KVM_REG_RISCV_CORE_REG(regs.pc) < reg_num &&
355 reg_num <= KVM_REG_RISCV_CORE_REG(regs.t6))
356 reg_val = ((unsigned long *)cntx)[reg_num];
375 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | local
404 kvm_riscv_vcpu_general_get_csr(struct kvm_vcpu *vcpu, unsigned long reg_num, unsigned long *out_val) argument
423 kvm_riscv_vcpu_general_set_csr(struct kvm_vcpu *vcpu, unsigned long reg_num, unsigned long reg_val) argument
445 kvm_riscv_vcpu_smstateen_set_csr(struct kvm_vcpu *vcpu, unsigned long reg_num, unsigned long reg_val) argument
459 kvm_riscv_vcpu_smstateen_get_csr(struct kvm_vcpu *vcpu, unsigned long reg_num, unsigned long *out_val) argument
479 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | local
521 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | local
557 riscv_vcpu_get_isa_ext_single(struct kvm_vcpu *vcpu, unsigned long reg_num, unsigned long *reg_val) argument
578 riscv_vcpu_set_isa_ext_single(struct kvm_vcpu *vcpu, unsigned long reg_num, unsigned long reg_val) argument
616 riscv_vcpu_get_isa_ext_multi(struct kvm_vcpu *vcpu, unsigned long reg_num, unsigned long *reg_val) argument
639 riscv_vcpu_set_isa_ext_multi(struct kvm_vcpu *vcpu, unsigned long reg_num, unsigned long reg_val, bool enable) argument
665 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | local
704 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | local
[all...]
H A Dvcpu_sbi.c172 unsigned long reg_num,
181 sext = riscv_vcpu_get_sbi_ext(vcpu, reg_num);
193 unsigned long reg_num,
199 sext = riscv_vcpu_get_sbi_ext(vcpu, reg_num);
210 unsigned long reg_num,
215 if (reg_num > KVM_REG_RISCV_SBI_MULTI_REG_LAST)
219 ext_id = i + reg_num * BITS_PER_LONG;
230 unsigned long reg_num,
235 if (reg_num > KVM_REG_RISCV_SBI_MULTI_REG_LAST)
239 ext_id = i + reg_num * BITS_PER_LON
171 riscv_vcpu_set_sbi_ext_single(struct kvm_vcpu *vcpu, unsigned long reg_num, unsigned long reg_val) argument
192 riscv_vcpu_get_sbi_ext_single(struct kvm_vcpu *vcpu, unsigned long reg_num, unsigned long *reg_val) argument
209 riscv_vcpu_set_sbi_ext_multi(struct kvm_vcpu *vcpu, unsigned long reg_num, unsigned long reg_val, bool enable) argument
229 riscv_vcpu_get_sbi_ext_multi(struct kvm_vcpu *vcpu, unsigned long reg_num, unsigned long *reg_val) argument
257 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | local
294 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | local
333 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | local
362 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | local
[all...]
/linux-master/arch/sparc/kernel/
H A Dpcr.c55 static u64 direct_pcr_read(unsigned long reg_num) argument
59 WARN_ON_ONCE(reg_num != 0);
64 static void direct_pcr_write(unsigned long reg_num, u64 val) argument
66 WARN_ON_ONCE(reg_num != 0);
70 static u64 direct_pic_read(unsigned long reg_num) argument
74 WARN_ON_ONCE(reg_num != 0);
79 static void direct_pic_write(unsigned long reg_num, u64 val) argument
81 WARN_ON_ONCE(reg_num != 0);
111 static void n2_pcr_write(unsigned long reg_num, u64 val) argument
115 WARN_ON_ONCE(reg_num !
144 n4_pcr_read(unsigned long reg_num) argument
153 n4_pcr_write(unsigned long reg_num, u64 val) argument
158 n4_pic_read(unsigned long reg_num) argument
169 n4_pic_write(unsigned long reg_num, u64 val) argument
195 n5_pcr_read(unsigned long reg_num) argument
204 n5_pcr_write(unsigned long reg_num, u64 val) argument
221 m7_pcr_read(unsigned long reg_num) argument
230 m7_pcr_write(unsigned long reg_num, u64 val) argument
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn32/
H A Dirq_service_dcn32.c209 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
210 .enable_reg = SRI(reg1, block, reg_num),\
212 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
214 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
215 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
217 .ack_reg = SRI(reg2, block, reg_num),\
219 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
221 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
237 #define hpd_int_entry(reg_num)\
238 [DC_IRQ_SOURCE_HPD1 + reg_num]
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn315/
H A Dirq_service_dcn315.c215 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
216 .enable_reg = SRI(reg1, block, reg_num),\
218 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
220 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
221 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
223 .ack_reg = SRI(reg2, block, reg_num),\
225 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
227 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
243 #define hpd_int_entry(reg_num)\
244 [DC_IRQ_SOURCE_HPD1 + reg_num]
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn302/
H A Dirq_service_dcn302.c195 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
196 .enable_reg = SRI(reg1, block, reg_num),\
197 .enable_mask = block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
199 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
200 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
202 .ack_reg = SRI(reg2, block, reg_num),\
203 .ack_mask = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
204 .ack_value = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
227 #define hpd_int_entry(reg_num)\
228 [DC_IRQ_SOURCE_HPD1 + reg_num]
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn30/
H A Dirq_service_dcn30.c220 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
221 .enable_reg = SRI(reg1, block, reg_num),\
223 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
225 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
226 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
228 .ack_reg = SRI(reg2, block, reg_num),\
230 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
232 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
248 #define hpd_int_entry(reg_num)\
249 [DC_IRQ_SOURCE_HPD1 + reg_num]
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn31/
H A Dirq_service_dcn31.c208 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
209 .enable_reg = SRI(reg1, block, reg_num),\
211 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
213 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
214 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
216 .ack_reg = SRI(reg2, block, reg_num),\
218 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
220 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
236 #define hpd_int_entry(reg_num)\
237 [DC_IRQ_SOURCE_HPD1 + reg_num]
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn314/
H A Dirq_service_dcn314.c210 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
211 .enable_reg = SRI(reg1, block, reg_num),\
213 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
215 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
216 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
218 .ack_reg = SRI(reg2, block, reg_num),\
220 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
222 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
238 #define hpd_int_entry(reg_num)\
239 [DC_IRQ_SOURCE_HPD1 + reg_num]
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn21/
H A Dirq_service_dcn21.c213 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
214 .enable_reg = SRI(reg1, block, reg_num),\
216 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
218 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
219 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
221 .ack_reg = SRI(reg2, block, reg_num),\
223 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
225 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
241 #define hpd_int_entry(reg_num)\
242 [DC_IRQ_SOURCE_HPD1 + reg_num]
[all...]
/linux-master/drivers/video/fbdev/via/
H A Dhw.h355 int reg_num; member in struct:iga2_shadow_hor_total
361 int reg_num; member in struct:iga2_shadow_hor_blank_end
367 int reg_num; member in struct:iga2_shadow_ver_total
373 int reg_num; member in struct:iga2_shadow_ver_addr
379 int reg_num; member in struct:iga2_shadow_ver_blank_start
385 int reg_num; member in struct:iga2_shadow_ver_blank_end
391 int reg_num; member in struct:iga2_shadow_ver_sync_start
397 int reg_num; member in struct:iga2_shadow_ver_sync_end
403 int reg_num; member in struct:iga1_fetch_count
409 int reg_num; member in struct:iga2_fetch_count
420 int reg_num; member in struct:iga1_starting_addr
425 int reg_num; member in struct:iga2_starting_addr
436 int reg_num; member in struct:lcd_pwd_seq_td0
441 int reg_num; member in struct:lcd_pwd_seq_td1
446 int reg_num; member in struct:lcd_pwd_seq_td2
451 int reg_num; member in struct:lcd_pwd_seq_td3
464 int reg_num; member in struct:_lcd_hor_scaling_factor
469 int reg_num; member in struct:_lcd_ver_scaling_factor
500 int reg_num; member in struct:iga1_fifo_depth_select
505 int reg_num; member in struct:iga1_fifo_threshold_select
510 int reg_num; member in struct:iga1_fifo_high_threshold_select
515 int reg_num; member in struct:iga1_display_queue_expire_num
520 int reg_num; member in struct:iga2_fifo_depth_select
525 int reg_num; member in struct:iga2_fifo_threshold_select
530 int reg_num; member in struct:iga2_fifo_high_threshold_select
535 int reg_num; member in struct:iga2_display_queue_expire_num
[all...]
/linux-master/arch/powerpc/platforms/powernv/
H A Dopal-fadump.h82 __be32 reg_num; member in struct:hdat_fadump_reg_entry
87 u32 reg_type, u32 reg_num,
91 if (reg_num < 32)
92 regs->gpr[reg_num] = reg_val;
96 switch (reg_num) {
141 be32_to_cpu(reg_entry->reg_num),
86 opal_fadump_set_regval_regnum(struct pt_regs *regs, u32 reg_type, u32 reg_num, u64 reg_val) argument
/linux-master/drivers/net/ethernet/arc/
H A Demac_mdio.c49 * @reg_num: PHY register to read.
56 static int arc_mdio_read(struct mii_bus *bus, int phy_addr, int reg_num) argument
63 0x60020000 | (phy_addr << 23) | (reg_num << 18));
71 dev_dbg(priv->dev, "arc_mdio_read(phy_addr=%i, reg_num=%x) = %x\n",
72 phy_addr, reg_num, value);
81 * @reg_num: PHY register to write to.
89 int reg_num, u16 value)
94 "arc_mdio_write(phy_addr=%i, reg_num=%x, value=%x)\n",
95 phy_addr, reg_num, value);
98 0x50020000 | (phy_addr << 23) | (reg_num << 1
88 arc_mdio_write(struct mii_bus *bus, int phy_addr, int reg_num, u16 value) argument
[all...]
/linux-master/drivers/irqchip/
H A Dirq-imx-irqsteer.c35 int reg_num; member in struct:irqsteer_data
44 return (data->reg_num - irqnum / 32 - 1);
55 val = readl_relaxed(data->regs + CHANMASK(idx, data->reg_num));
57 writel_relaxed(val, data->regs + CHANMASK(idx, data->reg_num));
69 val = readl_relaxed(data->regs + CHANMASK(idx, data->reg_num));
71 writel_relaxed(val, data->regs + CHANMASK(idx, data->reg_num));
129 if (hwirq >= data->reg_num * 32)
133 CHANSTATUS(idx, data->reg_num));
178 data->reg_num = irqs_num / 32;
182 sizeof(u32) * data->reg_num,
[all...]

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