irq/dcn10/irq_service_dcn10.c

200 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
201 	.enable_reg = SRI(reg1, block, reg_num),\
203 		block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
205 		block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
206 		~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
208 	.ack_reg = SRI(reg2, block, reg_num),\
210 		block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
212 		block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
214 #define hpd_int_entry(reg_num)\
215 	[DC_IRQ_SOURCE_HPD1 + reg_num] = {\
216 		IRQ_REG_ENTRY(HPD, reg_num,\
219 		.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
223 #define hpd_rx_int_entry(reg_num)\
224 	[DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
225 		IRQ_REG_ENTRY(HPD, reg_num,\
228 		.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
231 #define pflip_int_entry(reg_num)\
232 	[DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
233 		IRQ_REG_ENTRY(HUBPREQ, reg_num,\
242 #define vupdate_no_lock_int_entry(reg_num)\
243 	[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
244 		IRQ_REG_ENTRY(OTG, reg_num,\
250 #define vblank_int_entry(reg_num)\
251 	[DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
252 		IRQ_REG_ENTRY(OTG, reg_num,\
258 #define vline0_int_entry(reg_num)\
259 	[DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\
260 		IRQ_REG_ENTRY(OTG, reg_num,\
271 #define i2c_int_entry(reg_num) \
272 	[DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
274 #define dp_sink_int_entry(reg_num) \
275 	[DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
277 #define gpio_pad_int_entry(reg_num) \
278 	[DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
280 #define dc_underflow_int_entry(reg_num) \
281 	[DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()