irq/dcn32/irq_service_dcn32.c

209 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
210 	.enable_reg = SRI(reg1, block, reg_num),\
212 		block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
214 		block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
215 		~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
217 	.ack_reg = SRI(reg2, block, reg_num),\
219 		block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
221 		block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
237 #define hpd_int_entry(reg_num)\
238 	[DC_IRQ_SOURCE_HPD1 + reg_num] = {\
239 		IRQ_REG_ENTRY(HPD, reg_num,\
242 		.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
246 #define hpd_rx_int_entry(reg_num)\
247 	[DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
248 		IRQ_REG_ENTRY(HPD, reg_num,\
251 		.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
254 #define pflip_int_entry(reg_num)\
255 	[DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
256 		IRQ_REG_ENTRY(HUBPREQ, reg_num,\
265 #define vupdate_no_lock_int_entry(reg_num)\
266 	[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
267 		IRQ_REG_ENTRY(OTG, reg_num,\
273 #define vblank_int_entry(reg_num)\
274 	[DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
275 		IRQ_REG_ENTRY(OTG, reg_num,\
281 #define vline0_int_entry(reg_num)\
282 	[DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\
283 		IRQ_REG_ENTRY(OTG, reg_num,\
301 #define i2c_int_entry(reg_num) \
302 	[DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
304 #define dp_sink_int_entry(reg_num) \
305 	[DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
307 #define gpio_pad_int_entry(reg_num) \
308 	[DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
310 #define dc_underflow_int_entry(reg_num) \
311 	[DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()