irq/dcn21/irq_service_dcn21.c

213 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
214 	.enable_reg = SRI(reg1, block, reg_num),\
216 		block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
218 		block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
219 		~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
221 	.ack_reg = SRI(reg2, block, reg_num),\
223 		block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
225 		block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
241 #define hpd_int_entry(reg_num)\
242 	[DC_IRQ_SOURCE_HPD1 + reg_num] = {\
243 		IRQ_REG_ENTRY(HPD, reg_num,\
246 		.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
250 #define hpd_rx_int_entry(reg_num)\
251 	[DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
252 		IRQ_REG_ENTRY(HPD, reg_num,\
255 		.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
258 #define pflip_int_entry(reg_num)\
259 	[DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
260 		IRQ_REG_ENTRY(HUBPREQ, reg_num,\
269 #define vupdate_no_lock_int_entry(reg_num)\
270 	[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
271 		IRQ_REG_ENTRY(OTG, reg_num,\
277 #define vblank_int_entry(reg_num)\
278 	[DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
279 		IRQ_REG_ENTRY(OTG, reg_num,\
285 #define vline0_int_entry(reg_num)\
286 	[DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\
287 		IRQ_REG_ENTRY(OTG, reg_num,\
305 #define i2c_int_entry(reg_num) \
306 	[DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
308 #define dp_sink_int_entry(reg_num) \
309 	[DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
311 #define gpio_pad_int_entry(reg_num) \
312 	[DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
314 #define dc_underflow_int_entry(reg_num) \
315 	[DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()