irq/dcn302/irq_service_dcn302.c

195 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
196 		.enable_reg = SRI(reg1, block, reg_num),\
197 		.enable_mask = block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
199 				block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
200 				~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
202 		.ack_reg = SRI(reg2, block, reg_num),\
203 		.ack_mask = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
204 		.ack_value = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
227 #define hpd_int_entry(reg_num)\
228 		[DC_IRQ_SOURCE_HPD1 + reg_num] = {\
229 				IRQ_REG_ENTRY(HPD, reg_num,\
232 						.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
236 #define hpd_rx_int_entry(reg_num)\
237 		[DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
238 				IRQ_REG_ENTRY(HPD, reg_num,\
241 						.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
244 #define pflip_int_entry(reg_num)\
245 		[DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
246 				IRQ_REG_ENTRY(HUBPREQ, reg_num,\
255 #define vupdate_no_lock_int_entry(reg_num)\
256 	[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
257 		IRQ_REG_ENTRY(OTG, reg_num,\
263 #define vblank_int_entry(reg_num)\
264 	[DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
265 		IRQ_REG_ENTRY(OTG, reg_num,\
271 #define vline0_int_entry(reg_num)\
272 	[DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\
273 		IRQ_REG_ENTRY(OTG, reg_num,\
281 #define i2c_int_entry(reg_num) \
282 		[DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
284 #define dp_sink_int_entry(reg_num) \
285 		[DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
287 #define gpio_pad_int_entry(reg_num) \
288 		[DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
290 #define dc_underflow_int_entry(reg_num) \
291 		[DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()