Searched refs:reg_idx (Results 1 - 25 of 106) sorted by relevance

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/linux-master/drivers/staging/media/atomisp/pci/hive_isp_css_include/host/
H A Disys_irq_public.h30 const unsigned int reg_idx,
34 const unsigned int reg_idx);
H A Disys_stream2mmio_public.h60 * @param[in] reg_idx The offset address of the register.
67 const uint32_t reg_idx);
/linux-master/drivers/staging/media/atomisp/pci/css_2401_system/host/
H A Disys_irq_private.h69 const unsigned int reg_idx,
75 assert(reg_idx <= ISYS_IRQ_LEVEL_NO_REG_IDX);
77 reg_addr = ISYS_IRQ_BASE[isys_irqc_id] + (reg_idx * sizeof(hrt_data));
86 const unsigned int reg_idx)
92 assert(reg_idx <= ISYS_IRQ_LEVEL_NO_REG_IDX);
94 reg_addr = ISYS_IRQ_BASE[isys_irqc_id] + (reg_idx * sizeof(hrt_data));
67 isys_irqc_reg_store( const isys_irq_ID_t isys_irqc_id, const unsigned int reg_idx, const hrt_data value) argument
H A Disys_stream2mmio_private.h139 const uint32_t reg_idx)
147 (reg_bank_offset + reg_idx) * sizeof(hrt_data));
136 stream2mmio_reg_load( const stream2mmio_ID_t ID, const stream2mmio_sid_ID_t sid_id, const uint32_t reg_idx) argument
/linux-master/drivers/net/ethernet/intel/ixgbe/
H A Dixgbe_lib.c24 u16 reg_idx, pool; local
36 reg_idx = vmdq->offset * __ALIGN_MASK(1, ~vmdq->mask);
37 for (i = 0, pool = 0; i < adapter->num_rx_queues; i++, reg_idx++) {
39 if ((reg_idx & ~vmdq->mask) >= tcs) {
41 reg_idx = __ALIGN_MASK(reg_idx, ~vmdq->mask);
43 adapter->rx_ring[i]->reg_idx = reg_idx;
47 reg_idx = vmdq->offset * __ALIGN_MASK(1, ~vmdq->mask);
48 for (i = 0; i < adapter->num_tx_queues; i++, reg_idx
190 u16 reg_idx, pool; local
255 int i, reg_idx; local
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/linux-master/drivers/i2c/
H A Di2c-slave-testunit.c41 u8 reg_idx; member in struct:testunit_data
92 bool is_proc_call = tu->reg_idx == 3 && tu->regs[TU_REG_DATAL] == 1 &&
101 if (tu->reg_idx < TU_NUM_REGS)
102 tu->regs[tu->reg_idx] = *val;
106 if (tu->reg_idx <= TU_NUM_REGS)
107 tu->reg_idx++;
116 if (tu->reg_idx == TU_NUM_REGS) {
125 tu->reg_idx = 0;
/linux-master/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_hw_interrupts.h39 #define DPU_IRQ_IDX(reg_idx, offset) (1 + reg_idx * 32 + offset)
H A Ddpu_hw_interrupts.c242 int reg_idx; local
253 for (reg_idx = 0; reg_idx < MDP_INTR_MAX; reg_idx++) {
254 if (!test_bit(reg_idx, &intr->irq_mask))
258 irq_status = DPU_REG_READ(&intr->hw, intr->intr_set[reg_idx].status_off);
261 enable_mask = DPU_REG_READ(&intr->hw, intr->intr_set[reg_idx].en_off);
265 DPU_REG_WRITE(&intr->hw, intr->intr_set[reg_idx].clr_off,
278 irq_idx = DPU_IRQ_IDX(reg_idx, bit - 1);
302 int reg_idx; local
358 int reg_idx; local
447 int reg_idx; local
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/linux-master/drivers/pmdomain/renesas/
H A Drcar-gen4-sysc.c91 static int clear_irq_flags(unsigned int reg_idx, unsigned int isr_mask) argument
96 iowrite32(isr_mask, rcar_gen4_sysc_base + SYSCISCR(reg_idx));
98 ret = readl_poll_timeout_atomic(rcar_gen4_sysc_base + SYSCISCR(reg_idx),
112 unsigned int reg_idx, bit_idx; local
121 reg_idx = pdr / NUM_DOMAINS_EACH_REG;
130 iowrite32(ioread32(rcar_gen4_sysc_base + SYSCIER(reg_idx)) | isr_mask,
131 rcar_gen4_sysc_base + SYSCIER(reg_idx));
132 iowrite32(ioread32(rcar_gen4_sysc_base + SYSCIMR(reg_idx)) | isr_mask,
133 rcar_gen4_sysc_base + SYSCIMR(reg_idx));
135 ret = clear_irq_flags(reg_idx, isr_mas
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/linux-master/drivers/clocksource/
H A Dtimer-mediatek-cpux.c37 static u32 mtk_cpux_readl(u32 reg_idx, struct timer_of *to) argument
39 writel(reg_idx, timer_of_base(to) + CPUX_IDX_REG);
43 static void mtk_cpux_writel(u32 val, u32 reg_idx, struct timer_of *to) argument
45 writel(reg_idx, timer_of_base(to) + CPUX_IDX_REG);
/linux-master/drivers/irqchip/
H A Dirq-mvebu-sei.c59 u32 reg_idx = SEI_IRQ_REG_IDX(d->hwirq); local
62 sei->base + GICP_SECR(reg_idx));
68 u32 reg, reg_idx = SEI_IRQ_REG_IDX(d->hwirq); local
73 reg = readl_relaxed(sei->base + GICP_SEMR(reg_idx));
75 writel_relaxed(reg, sei->base + GICP_SEMR(reg_idx));
82 u32 reg, reg_idx = SEI_IRQ_REG_IDX(d->hwirq); local
87 reg = readl_relaxed(sei->base + GICP_SEMR(reg_idx));
89 writel_relaxed(reg, sei->base + GICP_SEMR(reg_idx));
354 u32 reg_idx; local
357 for (reg_idx
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H A Dirq-pruss-intc.c181 u8 ch, host, reg_idx; local
193 reg_idx = hwirq / 32;
197 pruss_intc_write_reg(intc, PRU_INTC_ESR(reg_idx), val);
198 pruss_intc_write_reg(intc, PRU_INTC_SECR(reg_idx), val);
224 u8 ch, host, reg_idx; local
241 reg_idx = hwirq / 32;
245 pruss_intc_write_reg(intc, PRU_INTC_ECR(reg_idx), val);
247 pruss_intc_write_reg(intc, PRU_INTC_SECR(reg_idx), val);
/linux-master/drivers/media/platform/mediatek/vcodec/common/
H A Dmtk_vcodec_util.c24 void __iomem *mtk_vcodec_get_reg_addr(void __iomem **reg_base, unsigned int reg_idx) argument
26 if (reg_idx >= NUM_MAX_VCODEC_REG_BASE) {
27 pr_err(MTK_DBG_V4L2_STR "Invalid arguments, reg_idx=%d", reg_idx);
30 return reg_base[reg_idx];
H A Dmtk_vcodec_util.h65 void __iomem *mtk_vcodec_get_reg_addr(void __iomem **reg_base, unsigned int reg_idx);
/linux-master/drivers/sh/intc/
H A Dhandle.c41 unsigned int *reg_idx,
48 while (mr && enum_id && *reg_idx < desc->hw.nr_mask_regs) {
49 mr = desc->hw.mask_regs + *reg_idx;
82 (*reg_idx)++;
109 unsigned int *reg_idx,
116 while (pr && enum_id && *reg_idx < desc->hw.nr_prio_regs) {
117 pr = desc->hw.prio_regs + *reg_idx;
151 (*reg_idx)++;
38 _intc_mask_data(struct intc_desc *desc, struct intc_desc_int *d, intc_enum enum_id, unsigned int *reg_idx, unsigned int *fld_idx) argument
106 _intc_prio_data(struct intc_desc *desc, struct intc_desc_int *d, intc_enum enum_id, unsigned int *reg_idx, unsigned int *fld_idx) argument
/linux-master/drivers/net/ethernet/intel/fm10k/
H A Dfm10k_pci.c875 u8 reg_idx = ring->reg_idx; local
878 fm10k_write_reg(hw, FM10K_TXDCTL(reg_idx), 0);
884 fm10k_write_reg(hw, FM10K_TDBAL(reg_idx), tdba & DMA_BIT_MASK(32));
885 fm10k_write_reg(hw, FM10K_TDBAH(reg_idx), tdba >> 32);
886 fm10k_write_reg(hw, FM10K_TDLEN(reg_idx), size);
889 fm10k_write_reg(hw, FM10K_TDH(reg_idx), 0);
890 fm10k_write_reg(hw, FM10K_TDT(reg_idx), 0);
893 ring->tail = &interface->uc_addr[FM10K_TDT(reg_idx)];
905 fm10k_write_reg(hw, FM10K_TXINT(reg_idx), txin
935 u8 reg_idx = ring->reg_idx; local
987 u8 reg_idx = ring->reg_idx; local
1075 u8 reg_idx = ring->reg_idx; local
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/linux-master/drivers/net/ethernet/wangxun/libwx/
H A Dwx_hw.c1294 j = ring->reg_idx;
1421 u8 reg_idx = ring->reg_idx; local
1426 wr32m(wx, WX_PX_RR_CFG(reg_idx),
1431 10, 100, true, wx, WX_PX_RR_CFG(reg_idx));
1437 reg_idx);
1444 u8 reg_idx = ring->reg_idx; local
1449 1000, 10000, true, wx, WX_PX_RR_CFG(reg_idx));
1455 reg_idx);
1462 u16 reg_idx = rx_ring->reg_idx; local
1482 u8 reg_idx = ring->reg_idx; local
1519 u16 reg_idx = ring->reg_idx; local
2181 u16 reg_idx = ring->reg_idx; local
2192 u16 reg_idx = ring->reg_idx; local
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/linux-master/include/linux/soc/mediatek/
H A Dmtk-cmdq.h106 * @reg_idx: the CMDQ internal register ID to cache read data
111 u16 reg_idx);
243 * @reg_idx: the CMDQ internal register ID
248 int cmdq_pkt_assign(struct cmdq_pkt *pkt, u16 reg_idx, u32 value);
316 u16 addr_low, u16 reg_idx)
372 static inline int cmdq_pkt_assign(struct cmdq_pkt *pkt, u16 reg_idx, u32 value) argument
315 cmdq_pkt_read_s(struct cmdq_pkt *pkt, u16 high_addr_reg_idx, u16 addr_low, u16 reg_idx) argument
/linux-master/drivers/bus/
H A Dimx-weim.c145 int reg_idx, num_regs; local
174 for (reg_idx = 0; reg_idx < num_regs; reg_idx++) {
177 reg_idx * OF_REG_SIZE, &cs_idx);
/linux-master/drivers/accel/habanalabs/goya/
H A Dgoya_coresight.c236 if (params->reg_idx >= ARRAY_SIZE(debug_stm_regs)) {
241 base_reg = debug_stm_regs[params->reg_idx] - CFG_BASE;
309 if (params->reg_idx >= ARRAY_SIZE(debug_etf_regs)) {
314 base_reg = debug_etf_regs[params->reg_idx] - CFG_BASE;
489 if (params->reg_idx >= ARRAY_SIZE(debug_funnel_regs)) {
494 base_reg = debug_funnel_regs[params->reg_idx] - CFG_BASE;
510 if (params->reg_idx >= ARRAY_SIZE(debug_bmon_regs)) {
515 base_reg = debug_bmon_regs[params->reg_idx] - CFG_BASE;
539 if (params->reg_idx != GOYA_BMON_PCIE_MSTR_RD &&
540 params->reg_idx !
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/linux-master/drivers/net/ethernet/intel/ixgbevf/
H A Dixgbevf_main.c200 u32 head = IXGBE_READ_REG(hw, IXGBE_VFTDH(ring->reg_idx));
201 u32 tail = IXGBE_READ_REG(hw, IXGBE_VFTDT(ring->reg_idx));
385 IXGBE_READ_REG(hw, IXGBE_VFTDH(tx_ring->reg_idx)),
386 IXGBE_READ_REG(hw, IXGBE_VFTDT(tx_ring->reg_idx)),
1365 ixgbevf_set_ivar(adapter, 0, ring->reg_idx, v_idx);
1368 ixgbevf_set_ivar(adapter, 1, ring->reg_idx, v_idx);
1691 u8 reg_idx = ring->reg_idx; local
1694 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
1697 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAL(reg_idx), tdb
1807 u8 reg_idx = ring->reg_idx; local
1834 u8 reg_idx = ring->reg_idx; local
1912 u8 reg_idx = ring->reg_idx; local
2520 u8 reg_idx = adapter->tx_ring[i]->reg_idx; local
2527 u8 reg_idx = adapter->xdp_ring[i]->reg_idx; local
2730 int reg_idx = txr_idx + xdp_idx; local
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/linux-master/drivers/hwtracing/coresight/
H A Dcoresight-cti-sysfs.c798 int used = 0, reg_idx; local
802 for (reg_idx = 0; reg_idx < nr_trig_max; reg_idx++) {
803 if (chan_mask & cfg->ctiinen[reg_idx])
804 used += sprintf(buf + used, "%d ", reg_idx);
818 int used = 0, reg_idx; local
822 for (reg_idx = 0; reg_idx < nr_trig_max; reg_idx
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/linux-master/drivers/accel/habanalabs/gaudi/
H A Dgaudi_coresight.c398 if (params->reg_idx >= ARRAY_SIZE(debug_stm_regs)) {
403 base_reg = debug_stm_regs[params->reg_idx] - CFG_BASE;
476 if (params->reg_idx >= ARRAY_SIZE(debug_etf_regs)) {
481 base_reg = debug_etf_regs[params->reg_idx] - CFG_BASE;
703 if (params->reg_idx >= ARRAY_SIZE(debug_funnel_regs)) {
708 base_reg = debug_funnel_regs[params->reg_idx] - CFG_BASE;
723 if (params->reg_idx >= ARRAY_SIZE(debug_bmon_regs)) {
728 base_reg = debug_bmon_regs[params->reg_idx] - CFG_BASE;
791 if (params->reg_idx >= ARRAY_SIZE(debug_spmu_regs)) {
796 base_reg = debug_spmu_regs[params->reg_idx]
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/linux-master/drivers/net/ethernet/intel/i40e/
H A Di40e_client.c148 u32 reg_idx; local
151 reg_idx = I40E_PFINT_LNKLSTN(qv_info->v_idx - 1);
152 wr32(&pf->hw, reg_idx, I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
567 u32 v_idx, i, reg_idx, reg; local
585 reg_idx = I40E_PFINT_LNKLSTN(v_idx - 1);
589 wr32(hw, reg_idx, I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
595 wr32(hw, reg_idx, reg);
/linux-master/sound/soc/codecs/
H A Dmt6351.c325 int idx, old_idx, offset, reg_idx; local
342 reg_idx = old_idx;
345 reg_idx = idx > old_idx ? reg_idx + 1 : reg_idx - 1;
348 if ((reg_idx >= 0 && reg_idx <= 0x12) || reg_idx == 0x1f) {
352 (reg_idx << 7) | reg_idx);
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