intel/fm10k/fm10k_pci.c

875 	u8 reg_idx = ring->reg_idx;
878 	fm10k_write_reg(hw, FM10K_TXDCTL(reg_idx), 0);
884 	fm10k_write_reg(hw, FM10K_TDBAL(reg_idx), tdba & DMA_BIT_MASK(32));
885 	fm10k_write_reg(hw, FM10K_TDBAH(reg_idx), tdba >> 32);
886 	fm10k_write_reg(hw, FM10K_TDLEN(reg_idx), size);
889 	fm10k_write_reg(hw, FM10K_TDH(reg_idx), 0);
890 	fm10k_write_reg(hw, FM10K_TDT(reg_idx), 0);
893 	ring->tail = &interface->uc_addr[FM10K_TDT(reg_idx)];
905 	fm10k_write_reg(hw, FM10K_TXINT(reg_idx), txint);
908 	fm10k_write_reg(hw, FM10K_PFVTCTL(reg_idx),
919 	fm10k_write_reg(hw, FM10K_TXDCTL(reg_idx), txdctl);
935 	u8 reg_idx = ring->reg_idx;
938 	if (fm10k_read_reg(hw, FM10K_TXDCTL(reg_idx)) & FM10K_TXDCTL_ENABLE)
944 		txdctl = fm10k_read_reg(hw, FM10K_TXDCTL(reg_idx));
948 			  "Could not enable Tx Queue %d\n", reg_idx);
987 	u8 reg_idx = ring->reg_idx;
990 	rxqctl = fm10k_read_reg(hw, FM10K_RXQCTL(reg_idx));
992 	fm10k_write_reg(hw, FM10K_RXQCTL(reg_idx), rxqctl);
998 	fm10k_write_reg(hw, FM10K_RDBAL(reg_idx), rdba & DMA_BIT_MASK(32));
999 	fm10k_write_reg(hw, FM10K_RDBAH(reg_idx), rdba >> 32);
1000 	fm10k_write_reg(hw, FM10K_RDLEN(reg_idx), size);
1003 	fm10k_write_reg(hw, FM10K_RDH(reg_idx), 0);
1004 	fm10k_write_reg(hw, FM10K_RDT(reg_idx), 0);
1007 	ring->tail = &interface->uc_addr[FM10K_RDT(reg_idx)];
1019 	fm10k_write_reg(hw, FM10K_SRRCTL(reg_idx), srrctl);
1029 	fm10k_write_reg(hw, FM10K_RXDCTL(reg_idx), rxdctl);
1044 	fm10k_write_reg(hw, FM10K_RXINT(reg_idx), rxint);
1047 	rxqctl = fm10k_read_reg(hw, FM10K_RXQCTL(reg_idx));
1049 	fm10k_write_reg(hw, FM10K_RXQCTL(reg_idx), rxqctl);
1075 		u8 reg_idx = ring->reg_idx;
1080 		fm10k_write_reg(hw, FM10K_RXDCTL(reg_idx), rxdctl);