Searched refs:reg_cfg (Results 1 - 21 of 21) sorted by relevance

/linux-master/drivers/clk/mediatek/
H A Dclk-fhctl.c62 readl(regs->reg_cfg), readl(regs->reg_updnlmt),
73 writel((readl(regs->reg_cfg) & ~(data->frddsx_en)), regs->reg_cfg);
74 writel((readl(regs->reg_cfg) & ~(data->sfstrx_en)), regs->reg_cfg);
75 writel((readl(regs->reg_cfg) & ~(data->fhctlx_en)), regs->reg_cfg);
79 r = readl(regs->reg_cfg);
82 writel(r, regs->reg_cfg);
84 r = readl(regs->reg_cfg);
[all...]
H A Dclk-pllfh.h50 void __iomem *reg_cfg; member in struct:fh_pll_regs
H A Dclk-pllfh.c132 regs->reg_cfg = fhx_base + offset->offset_cfg;
/linux-master/drivers/dma/
H A Dste_dma40_ll.c137 u32 reg_cfg,
172 lli->reg_cfg = reg_cfg;
182 lli->reg_cfg |= BIT(D40_SREG_CFG_TIM_POS);
184 lli->reg_cfg &= ~BIT(D40_SREG_CFG_TIM_POS);
214 dma_addr_t lli_phys, dma_addr_t first_phys, u32 reg_cfg,
250 reg_cfg, info, flags);
271 u32 reg_cfg,
299 reg_cfg, info, otherinfo, flags);
364 u32 reg_cfg,
133 d40_phy_fill_lli(struct d40_phy_lli *lli, dma_addr_t data, u32 data_size, dma_addr_t next_lli, u32 reg_cfg, struct stedma40_half_channel_info *info, unsigned int flags) argument
213 d40_phy_buf_to_lli(struct d40_phy_lli *lli, dma_addr_t addr, u32 size, dma_addr_t lli_phys, dma_addr_t first_phys, u32 reg_cfg, struct stedma40_half_channel_info *info, struct stedma40_half_channel_info *otherinfo, unsigned long flags) argument
266 d40_phy_sg_to_lli(struct scatterlist *sg, int sg_len, dma_addr_t target, struct d40_phy_lli *lli_sg, dma_addr_t lli_phys, u32 reg_cfg, struct stedma40_half_channel_info *info, struct stedma40_half_channel_info *otherinfo, unsigned long flags) argument
362 d40_log_fill_lli(struct d40_log_lli *lli, dma_addr_t data, u32 data_size, u32 reg_cfg, u32 data_width, unsigned int flags) argument
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H A Dste_dma40_ll.h332 * @reg_cfg: The configuration register.
345 u32 reg_cfg; member in struct:d40_phy_lli
446 u32 reg_cfg,
H A Dste_dma40.c835 writel(lli_src->reg_cfg, base + D40_CHAN_REG_SSCFG);
840 writel(lli_dst->reg_cfg, base + D40_CHAN_REG_SDCFG);
/linux-master/drivers/regulator/
H A Drt5759-regulator.c214 struct regulator_config reg_cfg; local
246 memset(&reg_cfg, 0, sizeof(reg_cfg));
247 reg_cfg.dev = priv->dev;
248 reg_cfg.of_node = np;
249 reg_cfg.init_data = of_get_regulator_init_data(priv->dev, np, reg_desc);
250 reg_cfg.regmap = priv->regmap;
252 rdev = devm_regulator_register(priv->dev, reg_desc, &reg_cfg);
H A Drtq6752-regulator.c222 struct regulator_config reg_cfg = {}; local
255 reg_cfg.dev = &i2c->dev;
256 reg_cfg.regmap = priv->regmap;
257 reg_cfg.driver_data = priv;
262 &reg_cfg);
/linux-master/drivers/gpu/drm/bridge/
H A Dlontium-lt9611.c95 const struct reg_sequence reg_cfg[] = { local
107 return regmap_multi_reg_write(lt9611->regmap, reg_cfg, ARRAY_SIZE(reg_cfg));
113 struct reg_sequence reg_cfg[] = { local
123 reg_cfg[1].def = 0x03;
125 return regmap_multi_reg_write(lt9611->regmap, reg_cfg, ARRAY_SIZE(reg_cfg));
176 const struct reg_sequence reg_cfg[] = { local
203 regmap_multi_reg_write(lt9611->regmap, reg_cfg, ARRAY_SIZE(reg_cfg));
226 const struct reg_sequence reg_cfg[] = { local
390 struct reg_sequence reg_cfg[] = { local
825 static const struct reg_sequence reg_cfg[] = { local
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/linux-master/include/linux/soc/ti/
H A Domap1-mux.h306 extern int omap_cfg_reg(unsigned long reg_cfg);
308 static inline int omap_cfg_reg(unsigned long reg_cfg) { return 0; } argument
/linux-master/drivers/ata/
H A Dpata_octeon_cf.c87 union cvmx_mio_boot_reg_cfgx reg_cfg; local
105 reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs));
106 reg_cfg.s.dmack = 0; /* Don't assert DMACK on access */
107 reg_cfg.s.tim_mult = tim_mult; /* Timing mutiplier */
108 reg_cfg.s.rd_dly = 0; /* Sample on falling edge of BOOT_OE */
109 reg_cfg.s.sam = 0; /* Don't combine write and output enable */
110 reg_cfg.s.we_ext = 0; /* No write enable extension */
111 reg_cfg.s.oe_ext = 0; /* No read enable extension */
112 reg_cfg.s.en = 1; /* Enable this region */
113 reg_cfg
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/linux-master/drivers/clk/sprd/
H A Dpll.h13 struct reg_cfg { struct
H A Dpll.c151 struct reg_cfg *cfg;
/linux-master/drivers/iommu/
H A Dsprd-iommu.c212 unsigned int reg_cfg; local
216 reg_cfg = SPRD_EX_CFG;
218 reg_cfg = SPRD_VAU_CFG;
222 sprd_iommu_update_bits(sdev, reg_cfg, mask, 0, val);
/linux-master/arch/arm/mach-davinci/
H A Dmux.h656 extern int davinci_cfg_reg(unsigned long reg_cfg);
660 static inline int davinci_cfg_reg(unsigned long reg_cfg) { return 0; } argument
/linux-master/drivers/net/wireless/realtek/rtw88/
H A Dsdio.c154 u32 reg_cfg; local
158 reg_cfg = rtw_sdio_to_bus_offset(rtwdev, REG_SDIO_INDIRECT_REG_CFG);
161 reg_cfg, &ret);
166 tmp = sdio_readb(rtwsdio->sdio_func, reg_cfg + 2, &ret);
/linux-master/drivers/leds/rgb/
H A Dleds-mt6370-rgb.c152 struct reg_cfg *reg_cfgs;
/linux-master/drivers/net/wireless/marvell/mwifiex/
H A Dsta_cmdresp.c1129 struct host_cmd_ds_chan_region_cfg *reg = &resp->params.reg_cfg;
H A Dfw.h2376 struct host_cmd_ds_chan_region_cfg reg_cfg; member in union:host_cmd_ds_command::__anon1065
H A Dsta_cmd.c1606 struct host_cmd_ds_chan_region_cfg *reg = &cmd->params.reg_cfg;
/linux-master/drivers/net/wireless/ralink/rt2x00/
H A Drt2800lib.c1316 u32 reg_cfg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG); local
1319 if (rt2x00_get_field32(reg_cfg, WPDMA_GLO_CFG_RX_DMA_BUSY) &&
1325 if (rt2x00_get_field32(reg_cfg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&

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