Searched refs:pwmchip_parent (Results 1 - 25 of 40) sorted by relevance

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/linux-master/drivers/pwm/
H A Dpwm-ab8500.c94 ret = abx500_mask_and_set_register_interruptible(pwmchip_parent(chip),
99 dev_err(pwmchip_parent(chip), "%s: Failed to disable PWM, Error %d\n",
117 ret = abx500_set_register_interruptible(pwmchip_parent(chip), AB8500_MISC,
122 ret = abx500_set_register_interruptible(pwmchip_parent(chip), AB8500_MISC,
128 ret = abx500_mask_and_set_register_interruptible(pwmchip_parent(chip),
132 dev_err(pwmchip_parent(chip), "%s: Failed to enable PWM, Error %d\n",
146 ret = abx500_get_register_interruptible(pwmchip_parent(chip), AB8500_MISC,
159 ret = abx500_get_register_interruptible(pwmchip_parent(chip), AB8500_MISC,
165 ret = abx500_get_register_interruptible(pwmchip_parent(chip), AB8500_MISC,
H A Dpwm-twl.c88 dev_err(pwmchip_parent(chip), "%s: Failed to configure PWM\n", pwm->label);
102 dev_err(pwmchip_parent(chip), "%s: Failed to read GPBR1\n", pwm->label);
110 dev_err(pwmchip_parent(chip), "%s: Failed to enable PWM\n", pwm->label);
116 dev_err(pwmchip_parent(chip), "%s: Failed to enable PWM\n", pwm->label);
132 dev_err(pwmchip_parent(chip), "%s: Failed to read GPBR1\n", pwm->label);
140 dev_err(pwmchip_parent(chip), "%s: Failed to disable PWM\n", pwm->label);
146 dev_err(pwmchip_parent(chip), "%s: Failed to disable PWM\n", pwm->label);
169 dev_err(pwmchip_parent(chip), "%s: Failed to read PMBR1\n", pwm->label);
183 dev_err(pwmchip_parent(chip), "%s: Failed to request PWM\n", pwm->label);
204 dev_err(pwmchip_parent(chi
[all...]
H A Dpwm-twl-led.c102 dev_err(pwmchip_parent(chip), "%s: Failed to configure PWM\n", pwm->label);
116 dev_err(pwmchip_parent(chip), "%s: Failed to read LEDEN\n", pwm->label);
124 dev_err(pwmchip_parent(chip), "%s: Failed to enable PWM\n", pwm->label);
141 dev_err(pwmchip_parent(chip), "%s: Failed to read LEDEN\n", pwm->label);
149 dev_err(pwmchip_parent(chip), "%s: Failed to disable PWM\n", pwm->label);
205 dev_err(pwmchip_parent(chip), "%s: Failed to configure PWM\n", pwm->label);
219 dev_err(pwmchip_parent(chip), "%s: Failed to read PWM_CTRL2\n",
229 dev_err(pwmchip_parent(chip), "%s: Failed to enable PWM\n", pwm->label);
246 dev_err(pwmchip_parent(chip), "%s: Failed to read PWM_CTRL2\n",
256 dev_err(pwmchip_parent(chi
[all...]
H A Dpwm-stmpe.c46 dev_dbg(pwmchip_parent(chip), "error reading PWM#%u control\n",
55 dev_dbg(pwmchip_parent(chip), "error writing PWM#%u control\n",
72 dev_dbg(pwmchip_parent(chip), "error reading PWM#%u control\n",
81 dev_dbg(pwmchip_parent(chip), "error writing PWM#%u control\n",
127 dev_err(pwmchip_parent(chip), "unable to connect PWM#%u to pin\n",
152 dev_dbg(pwmchip_parent(chip), "PWM#%u: config duty %d ns, period %d ns\n",
218 dev_dbg(pwmchip_parent(chip),
235 dev_dbg(pwmchip_parent(chip), "error writing register %02x: %d\n",
244 dev_dbg(pwmchip_parent(chip), "error writing register %02x: %d\n",
257 dev_dbg(pwmchip_parent(chi
[all...]
H A Dpwm-omap-dmtimer.c156 dev_dbg(pwmchip_parent(chip), "requested duty cycle: %d ns, period: %d ns\n",
165 dev_err(pwmchip_parent(chip), "invalid pmtimer fclk\n");
171 dev_err(pwmchip_parent(chip), "invalid pmtimer fclk rate\n");
175 dev_dbg(pwmchip_parent(chip), "clk rate: %luHz\n", clk_rate);
197 dev_info(pwmchip_parent(chip),
204 dev_dbg(pwmchip_parent(chip),
207 dev_dbg(pwmchip_parent(chip), "using minimum of 1 clock cycle\n");
210 dev_dbg(pwmchip_parent(chip),
213 dev_dbg(pwmchip_parent(chip), "using maximum of 1 clock cycle less than period\n");
217 dev_dbg(pwmchip_parent(chi
[all...]
H A Dpwm-lpss.c109 dev_err(pwmchip_parent(pwm->chip), "PWM_SW_UPDATE was not cleared\n");
117 dev_err(pwmchip_parent(pwm->chip), "PWM_SW_UPDATE is still set, skipping update\n");
193 pm_runtime_get_sync(pwmchip_parent(chip));
196 pm_runtime_put(pwmchip_parent(chip));
202 pm_runtime_put(pwmchip_parent(chip));
216 pm_runtime_get_sync(pwmchip_parent(chip));
238 pm_runtime_put(pwmchip_parent(chip));
H A Dpwm-dwc-core.c108 pm_runtime_get_sync(pwmchip_parent(chip));
113 pm_runtime_put_sync(pwmchip_parent(chip));
127 pm_runtime_get_sync(pwmchip_parent(chip));
152 pm_runtime_put_sync(pwmchip_parent(chip));
H A Dpwm-tiecap.c72 pm_runtime_get_sync(pwmchip_parent(chip));
102 pm_runtime_put_sync(pwmchip_parent(chip));
113 pm_runtime_get_sync(pwmchip_parent(chip));
126 pm_runtime_put_sync(pwmchip_parent(chip));
137 pm_runtime_get_sync(pwmchip_parent(chip));
164 pm_runtime_put_sync(pwmchip_parent(chip));
275 pm_runtime_get_sync(pwmchip_parent(chip));
279 pm_runtime_put_sync(pwmchip_parent(chip));
H A Dcore.c74 dev_warn(pwmchip_parent(chip), ".apply ignored .polarity\n");
80 dev_warn(pwmchip_parent(chip),
85 dev_warn(pwmchip_parent(chip),
94 dev_warn(pwmchip_parent(chip),
101 dev_warn(pwmchip_parent(chip),
107 dev_warn(pwmchip_parent(chip),
115 dev_err(pwmchip_parent(chip), "failed to reapply current setting\n");
130 dev_err(pwmchip_parent(chip),
321 const char *chip_name = dev_name(pwmchip_parent(chip));
517 if (!pwmchip_parent(chi
[all...]
H A Dpwm-jz4740.c42 device_property_read_u32(pwmchip_parent(chip)->parent,
61 clk = clk_get(pwmchip_parent(chip), name);
63 dev_err(pwmchip_parent(chip),
152 dev_err(pwmchip_parent(chip), "Unable to round rate: %ld\n", rate);
173 dev_err(pwmchip_parent(chip), "Unable to set rate: %d\n", err);
H A Dpwm-tiehrpwm.c258 dev_err(pwmchip_parent(chip),
270 dev_err(pwmchip_parent(chip), "Unsupported values\n");
274 pm_runtime_get_sync(pwmchip_parent(chip));
301 pm_runtime_put_sync(pwmchip_parent(chip));
325 pm_runtime_get_sync(pwmchip_parent(chip));
348 dev_err(pwmchip_parent(chip), "Failed to enable TBCLK for %s: %d\n",
349 dev_name(pwmchip_parent(chip)), ret);
387 pm_runtime_put_sync(pwmchip_parent(chip));
395 dev_warn(pwmchip_parent(chip), "Removing PWM device without disabling\n");
396 pm_runtime_put_sync(pwmchip_parent(chi
[all...]
H A Dpwm-rz-mtu3.c220 rc = pm_runtime_resume_and_get(pwmchip_parent(chip));
266 pm_runtime_put_sync(pwmchip_parent(chip));
275 rc = pm_runtime_resume_and_get(pwmchip_parent(chip));
308 pm_runtime_put(pwmchip_parent(chip));
363 rc = pm_runtime_resume_and_get(pwmchip_parent(chip));
400 pm_runtime_put(pwmchip_parent(chip));
469 pm_runtime_disable(pwmchip_parent(chip));
470 pm_runtime_set_suspended(pwmchip_parent(chip));
H A Dpwm-img.c100 dev_err(pwmchip_parent(chip), "configured period not in range\n");
121 dev_err(pwmchip_parent(chip),
128 ret = pm_runtime_resume_and_get(pwmchip_parent(chip));
142 pm_runtime_mark_last_busy(pwmchip_parent(chip));
143 pm_runtime_put_autosuspend(pwmchip_parent(chip));
154 ret = pm_runtime_resume_and_get(pwmchip_parent(chip));
178 pm_runtime_mark_last_busy(pwmchip_parent(chip));
179 pm_runtime_put_autosuspend(pwmchip_parent(chip));
H A Dpwm-pca9685.c112 struct device *dev = pwmchip_parent(chip);
125 struct device *dev = pwmchip_parent(chip);
256 pm_runtime_get_sync(pwmchip_parent(chip));
281 pm_runtime_put(pwmchip_parent(chip));
315 struct device *dev = pwmchip_parent(chip);
352 struct device *dev = pwmchip_parent(chip);
381 dev_err(pwmchip_parent(chip), "pwm not changed: period out of bounds!\n");
393 dev_err(pwmchip_parent(chip),
489 pm_runtime_get_sync(pwmchip_parent(chip));
503 pm_runtime_put(pwmchip_parent(chi
[all...]
H A Dpwm-tegra.c158 err = dev_pm_opp_set_rate(pwmchip_parent(chip), required_clk_rate);
194 err = pm_runtime_resume_and_get(pwmchip_parent(chip));
206 pm_runtime_put(pwmchip_parent(chip));
217 rc = pm_runtime_resume_and_get(pwmchip_parent(chip));
237 pm_runtime_put_sync(pwmchip_parent(chip));
H A Dpwm-samsung.c199 dev_warn(pwmchip_parent(chip),
204 dev_dbg(pwmchip_parent(chip), "tin parent at %lu\n", rate);
234 dev_warn(pwmchip_parent(chip),
328 dev_dbg(pwmchip_parent(chip), "duty_ns=%d, period_ns=%d (%u)\n",
333 dev_dbg(pwmchip_parent(chip), "tin_rate=%lu\n", tin_rate);
357 dev_dbg(pwmchip_parent(chip), "tin_ns=%u, tcmp=%u/%u\n", tin_ns, tcmp, tcnt);
369 dev_dbg(pwmchip_parent(chip), "Forcing manual update");
511 struct device_node *np = pwmchip_parent(chip)->of_node;
525 dev_err(pwmchip_parent(chip),
H A Dpwm-crc.c56 struct device *dev = pwmchip_parent(chip);
126 struct device *dev = pwmchip_parent(chip);
H A Dpwm-meson.c123 struct device *dev = pwmchip_parent(chip);
171 dev_err(pwmchip_parent(chip), "invalid source clock frequency\n");
175 dev_dbg(pwmchip_parent(chip), "fin_freq: %lu Hz\n", fin_freq);
179 dev_err(pwmchip_parent(chip), "unable to get period cnt\n");
183 dev_dbg(pwmchip_parent(chip), "period=%llu cnt=%u\n", period, cnt);
194 dev_dbg(pwmchip_parent(chip), "duty=%llu duty_cnt=%u\n", duty, duty_cnt);
218 dev_err(pwmchip_parent(chip), "setting clock rate failed\n");
410 struct device *dev = pwmchip_parent(chip);
H A Dpwm-ep93xx.c48 struct platform_device *pdev = to_platform_device(pwmchip_parent(chip));
55 struct platform_device *pdev = to_platform_device(pwmchip_parent(chip));
H A Dpwm-mtk-disp.c93 dev_err(pwmchip_parent(chip), "Can't enable mdp->clk_main: %pe\n",
100 dev_err(pwmchip_parent(chip), "Can't enable mdp->clk_mm: %pe\n",
183 dev_err(pwmchip_parent(chip), "Can't enable mdp->clk_main: %pe\n", ERR_PTR(err));
189 dev_err(pwmchip_parent(chip), "Can't enable mdp->clk_mm: %pe\n", ERR_PTR(err));
H A Dpwm-vt8500.c68 dev_warn(pwmchip_parent(chip), "Waiting for status bits 0x%x to clear timed out\n",
83 dev_err(pwmchip_parent(chip), "failed to enable clock\n");
134 dev_err(pwmchip_parent(chip), "failed to enable clock\n");
H A Dpwm-stm32-lp.c63 dev_dbg(pwmchip_parent(chip), "Can't reach %llu ns\n", state->period);
71 dev_err(pwmchip_parent(chip), "max prescaler exceeded\n");
132 dev_err(pwmchip_parent(chip), "ARR/CMP registers write issue\n");
H A Dpwm-imx27.c150 dev_warn(pwmchip_parent(chip), "can't set polarity, output disconnected");
182 struct device *dev = pwmchip_parent(chip);
201 struct device *dev = pwmchip_parent(chip);
H A Dpwm-atmel.c212 dev_err(pwmchip_parent(chip), "pres exceeds the maximum value\n");
320 dev_err(pwmchip_parent(chip),
332 dev_err(pwmchip_parent(chip), "failed to enable clock\n");
480 dev_err(pwmchip_parent(chip),
/linux-master/drivers/staging/greybus/
H A Dpwm.c53 gbphy_dev = to_gbphy_dev(pwmchip_parent(chip));
75 gbphy_dev = to_gbphy_dev(pwmchip_parent(chip));
100 gbphy_dev = to_gbphy_dev(pwmchip_parent(chip));
124 gbphy_dev = to_gbphy_dev(pwmchip_parent(chip));
146 gbphy_dev = to_gbphy_dev(pwmchip_parent(chip));
171 gbphy_dev = to_gbphy_dev(pwmchip_parent(chip));
185 dev_warn(pwmchip_parent(chip), "freeing PWM device without disabling\n");

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