| /linux-master/drivers/clk/samsung/ |
| H A D | clk-cpu.h | 32 * @prate: frequency of the primary parent clock (in KHz)
38 * specified in @prate. The @prate is the frequency of the primary parent clock.
43 unsigned long prate; member in struct:exynos_cpuclk_cfg_data
|
| /linux-master/drivers/gpu/drm/mcde/ |
| H A D | mcde_clk_div.c | 45 unsigned long *prate, bool set_parent)
59 this_prate = *prate;
70 *prate = best_prate;
75 unsigned long *prate)
77 int div = mcde_clk_div_choose_div(hw, rate, prate, true);
79 return DIV_ROUND_UP_ULL(*prate, div);
83 unsigned long prate)
96 return DIV_ROUND_UP_ULL(prate, 2);
100 return prate;
106 return DIV_ROUND_UP_ULL(prate, di
44 mcde_clk_div_choose_div(struct clk_hw *hw, unsigned long rate, unsigned long *prate, bool set_parent) argument
74 mcde_clk_div_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) argument
82 mcde_clk_div_recalc_rate(struct clk_hw *hw, unsigned long prate) argument
109 mcde_clk_div_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate) argument
[all...] |
| /linux-master/drivers/clk/spear/ |
| H A D | clk-frac-synth.c | 41 static unsigned long frac_calc_rate(struct clk_hw *hw, unsigned long prate, argument
47 prate /= 10000;
48 prate <<= 14;
49 prate /= (2 * rtbl[index].div);
50 prate *= 10000;
52 return prate;
56 unsigned long *prate)
61 return clk_round_rate_index(hw, drate, *prate, frac_calc_rate,
93 unsigned long prate)
100 clk_round_rate_index(hw, drate, prate, frac_calc_rat
55 clk_frac_round_rate(struct clk_hw *hw, unsigned long drate, unsigned long *prate) argument
92 clk_frac_set_rate(struct clk_hw *hw, unsigned long drate, unsigned long prate) argument
[all...] |
| H A D | clk-vco-pll.c | 67 unsigned long prate, int index, unsigned long *pll_rate)
69 unsigned long rate = prate;
82 unsigned long *prate, int *index)
89 if (!prate) {
90 pr_err("%s: prate is must for pll clk\n", __func__);
96 vco_prev_rate = *prate;
97 *prate = pll_calc_rate(pll->vco->rtbl, vco_parent_rate, *index,
103 *prate = vco_prev_rate;
114 unsigned long *prate)
118 return clk_pll_round_rate_index(hw, drate, prate,
66 pll_calc_rate(struct pll_rate_tbl *rtbl, unsigned long prate, int index, unsigned long *pll_rate) argument
81 clk_pll_round_rate_index(struct clk_hw *hw, unsigned long drate, unsigned long *prate, int *index) argument
113 clk_pll_round_rate(struct clk_hw *hw, unsigned long drate, unsigned long *prate) argument
141 clk_pll_set_rate(struct clk_hw *hw, unsigned long drate, unsigned long prate) argument
171 vco_calc_rate(struct clk_hw *hw, unsigned long prate, int index) argument
179 clk_vco_round_rate(struct clk_hw *hw, unsigned long drate, unsigned long *prate) argument
227 clk_vco_set_rate(struct clk_hw *hw, unsigned long drate, unsigned long prate) argument
[all...] |
| H A D | clk-gpt-synth.c | 31 static unsigned long gpt_calc_rate(struct clk_hw *hw, unsigned long prate, argument
37 prate /= ((1 << (rtbl[index].nscale + 1)) * (rtbl[index].mscale + 1));
39 return prate;
43 unsigned long *prate)
48 return clk_round_rate_index(hw, drate, *prate, gpt_calc_rate,
78 unsigned long prate)
85 clk_round_rate_index(hw, drate, prate, gpt_calc_rate, gpt->rtbl_cnt,
42 clk_gpt_round_rate(struct clk_hw *hw, unsigned long drate, unsigned long *prate) argument
77 clk_gpt_set_rate(struct clk_hw *hw, unsigned long drate, unsigned long prate) argument
|
| H A D | clk-aux-synth.c | 41 static unsigned long aux_calc_rate(struct clk_hw *hw, unsigned long prate, argument
48 return (((prate / 10000) * rtbl[index].xscale) /
53 unsigned long *prate)
58 return clk_round_rate_index(hw, drate, *prate, aux_calc_rate,
97 unsigned long prate)
104 clk_round_rate_index(hw, drate, prate, aux_calc_rate, aux->rtbl_cnt,
52 clk_aux_round_rate(struct clk_hw *hw, unsigned long drate, unsigned long *prate) argument
96 clk_aux_set_rate(struct clk_hw *hw, unsigned long drate, unsigned long prate) argument
|
| /linux-master/drivers/clk/qcom/ |
| H A D | clk-regmap-divider.c | 19 unsigned long *prate)
29 return divider_ro_round_rate(hw, rate, prate, NULL, divider->width,
34 unsigned long *prate)
38 return divider_round_rate(hw, rate, prate, NULL, divider->width,
18 div_round_ro_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) argument
33 div_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) argument
|
| H A D | clk-regmap-mux-div.c | 125 unsigned long prate, u32 src)
187 unsigned long rate, unsigned long prate)
191 return __mux_div_set_rate_and_parent(hw, rate, prate, md->src);
195 unsigned long prate, u8 index)
199 return __mux_div_set_rate_and_parent(hw, rate, prate,
203 static unsigned long mux_div_recalc_rate(struct clk_hw *hw, unsigned long prate) argument
124 __mux_div_set_rate_and_parent(struct clk_hw *hw, unsigned long rate, unsigned long prate, u32 src) argument
186 mux_div_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate) argument
194 mux_div_set_rate_and_parent(struct clk_hw *hw, unsigned long rate, unsigned long prate, u8 index) argument
|
| H A D | clk-alpha-pll.c | 583 alpha_pll_calc_rate(u64 prate, u32 l, u32 a, u32 alpha_width) argument
585 return (prate * l) + ((prate * a) >> ALPHA_SHIFT(alpha_width));
589 alpha_pll_round_rate(unsigned long rate, unsigned long prate, u32 *l, u64 *a, argument
596 remainder = do_div(quotient, prate);
607 remainder = do_div(quotient, prate);
613 return alpha_pll_calc_rate(prate, *l, *a, alpha_width);
633 u64 a = 0, prate = parent_rate; local
654 return alpha_pll_calc_rate(prate, l, a, alpha_width);
712 unsigned long prate,
711 __clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate, int (*is_enabled)(struct clk_hw *)) argument
750 clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate) argument
757 clk_alpha_pll_hwfsm_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate) argument
764 clk_alpha_pll_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) argument
783 alpha_huayra_pll_calc_rate(u64 prate, u32 l, u32 a) argument
796 alpha_huayra_pll_round_rate(unsigned long rate, unsigned long prate, u32 *l, u32 *a) argument
883 alpha_pll_huayra_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate) argument
926 alpha_pll_huayra_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) argument
1115 clk_alpha_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) argument
1131 clk_alpha_pll_postdiv_round_ro_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) argument
1330 alpha_pll_fabia_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate) argument
1473 clk_trion_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) argument
1510 clk_alpha_pll_postdiv_fabia_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) argument
1644 __alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate, u32 latch_bit, u32 latch_ack) argument
1691 alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate) argument
1744 clk_alpha_pll_agera_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate) argument
1879 alpha_pll_lucid_5lpe_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate) argument
2064 clk_zonda_pll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate) argument
2389 clk_rivian_evo_pll_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) argument
2482 clk_alpha_pll_stromer_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate) argument
2528 clk_alpha_pll_stromer_plus_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate) argument
[all...] |
| /linux-master/drivers/clk/meson/ |
| H A D | sclk-div.c | 42 unsigned long prate, int maxdiv)
44 int div = DIV_ROUND_CLOSEST_ULL((u64)prate, rate);
50 unsigned long *prate,
64 return sclk_div_getdiv(hw, rate, *prate, maxdiv);
78 if (rate * i == *prate)
94 *prate = best_parent;
168 unsigned long prate)
174 sclk->cached_div = sclk_div_getdiv(hw, rate, prate, maxdiv);
183 unsigned long prate)
188 return DIV_ROUND_UP_ULL((u64)prate, scl
41 sclk_div_getdiv(struct clk_hw *hw, unsigned long rate, unsigned long prate, int maxdiv) argument
49 sclk_div_bestdiv(struct clk_hw *hw, unsigned long rate, unsigned long *prate, struct meson_sclk_div_data *sclk) argument
167 sclk_div_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate) argument
182 sclk_div_recalc_rate(struct clk_hw *hw, unsigned long prate) argument
[all...] |
| H A D | clk-cpu-dyndiv.c | 20 unsigned long prate)
25 return divider_recalc_rate(hw, prate,
19 meson_clk_cpu_dyndiv_recalc_rate(struct clk_hw *hw, unsigned long prate) argument
|
| /linux-master/drivers/clk/imx/ |
| H A D | clk-pll14xx.c | 105 int sdiv, int kdiv, unsigned long prate)
107 u64 fout = prate;
119 unsigned long rate, unsigned long prate)
123 /* calc kdiv = round(rate * pdiv * 65536 * 2^sdiv / prate) - (mdiv * 65536) */
124 kdiv = ((rate * ((pdiv * 65536) << sdiv) + prate / 2) / prate) - (mdiv * 65536);
130 unsigned long prate, struct imx_pll14xx_rate_table *t)
145 * fvco = (m * 65536 + k) * prate / (p * 65536)
146 * fout = (m * 65536 + k) * prate / (p * 65536) / (1 << sdiv)
153 clk_hw_get_name(&pll->hw), prate, rat
104 pll14xx_calc_rate(struct clk_pll14xx *pll, int mdiv, int pdiv, int sdiv, int kdiv, unsigned long prate) argument
118 pll1443x_calc_kdiv(int mdiv, int pdiv, int sdiv, unsigned long rate, unsigned long prate) argument
129 imx_pll14xx_calc_settings(struct clk_pll14xx *pll, unsigned long rate, unsigned long prate, struct imx_pll14xx_rate_table *t) argument
217 clk_pll1416x_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) argument
233 clk_pll1443x_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) argument
284 clk_pll1416x_set_rate(struct clk_hw *hw, unsigned long drate, unsigned long prate) argument
350 clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate, unsigned long prate) argument
[all...] |
| H A D | clk-pllv3.c | 121 unsigned long *prate)
123 unsigned long parent_rate = *prate;
169 unsigned long *prate)
171 unsigned long parent_rate = *prate;
230 unsigned long *prate)
232 unsigned long parent_rate = *prate;
359 unsigned long *prate)
361 struct clk_pllv3_vf610_mf mf = clk_pllv3_vf610_rate_to_mf(*prate, rate);
363 return clk_pllv3_vf610_mf_to_rate(*prate, mf);
120 clk_pllv3_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) argument
168 clk_pllv3_sys_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) argument
229 clk_pllv3_av_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) argument
358 clk_pllv3_vf610_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) argument
|
| /linux-master/drivers/clk/renesas/ |
| H A D | rcar-gen3-cpg.c | 70 unsigned long prate; local
72 prate = req->best_parent_rate * pll_clk->fixed_mult;
73 min_mult = max(div64_ul(req->min_rate, prate), 1ULL);
74 max_mult = min(div64_ul(req->max_rate, prate), 128ULL);
78 mult = DIV_ROUND_CLOSEST_ULL(req->rate, prate);
81 req->rate = prate * mult;
194 unsigned long rate, prate; local
199 prate = zclk->max_rate;
202 prate = rate;
205 prate * zcl
[all...] |
| H A D | rcar-gen4-cpg.c | 85 unsigned long prate; local
87 prate = req->best_parent_rate * 2;
88 min_mult = max(div64_ul(req->min_rate, prate), 1ULL);
89 max_mult = min(div64_ul(req->max_rate, prate), 256ULL);
93 mult = DIV_ROUND_CLOSEST_ULL(req->rate, prate);
96 req->rate = prate * mult;
215 unsigned long rate, prate; local
220 prate = zclk->max_rate;
223 prate = rate;
226 prate * zcl
[all...] |
| H A D | clk-div6.c | 106 unsigned long prate, calc_rate, diff, best_rate, best_prate; local
117 prate = clk_hw_get_rate(parent);
118 if (!prate)
121 min_div = max(DIV_ROUND_UP(prate, req->max_rate), 1UL);
122 max_div = req->min_rate ? min(prate / req->min_rate, 64UL) : 64;
126 div = cpg_div6_clock_calc_div(req->rate, prate);
128 calc_rate = prate / div;
134 best_prate = prate;
|
| /linux-master/drivers/clk/sunxi-ng/ |
| H A D | ccu_gate.c | 91 unsigned long *prate)
104 *prate = clk_hw_round_rate(clk_hw_get_parent(hw), best_parent);
107 return *prate / div;
90 ccu_gate_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) argument
|
| /linux-master/drivers/clk/x86/ |
| H A D | clk-cgu.c | 137 unsigned long *prate)
141 return divider_round_rate(hw, rate, prate, divider->table,
147 unsigned long prate)
152 value = divider_get_val(rate, prate, divider->table,
396 u64 prate; local
404 prate = (u64)parent_rate;
405 do_div(prate, div0);
406 do_div(prate, div1);
409 do_div(prate, ddiv->div);
410 prate *
136 lgm_clk_divider_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) argument
146 lgm_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate) argument
462 lgm_clk_ddiv_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate) argument
491 lgm_clk_ddiv_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) argument
[all...] |
| H A D | clk-cgu-pll.c | 22 * rate = (prate * mult + (prate * frac) / frac_div) / div
25 lgm_pll_calc_rate(unsigned long prate, unsigned int mult, argument
30 rate64 = prate;
40 static unsigned long lgm_pll_recalc_rate(struct clk_hw *hw, unsigned long prate) argument
52 return lgm_pll_calc_rate(prate, mult, div, frac, BIT(24));
|
| /linux-master/drivers/rtc/ |
| H A D | rtc-ac100.c | 120 unsigned long prate)
128 if (prate != AC100_RTC_32K_RATE) {
131 prate = divider_recalc_rate(hw, prate, div,
138 return divider_recalc_rate(hw, prate, div, NULL,
144 unsigned long prate)
149 if (prate == AC100_RTC_32K_RATE)
150 return divider_round_rate(hw, rate, &prate, NULL,
155 tmp_prate = DIV_ROUND_UP(prate, ac100_clkout_prediv[i].val);
178 unsigned long tmp, prate; local
119 ac100_clkout_recalc_rate(struct clk_hw *hw, unsigned long prate) argument
143 ac100_clkout_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate) argument
222 ac100_clkout_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate) argument
[all...] |
| /linux-master/drivers/clk/ |
| H A D | clk-vt8500.c | 132 unsigned long *prate)
140 divisor = *prate / rate;
142 /* If prate / rate would be decimal, incr the divisor */
143 if (rate * divisor < *prate)
154 return *prate / divisor;
598 unsigned long *prate)
607 ret = vt8500_find_pll_bits(rate, *prate, &mul, &div1);
609 round_rate = VT8500_BITS_TO_FREQ(*prate, mul, div1);
612 ret = wm8650_find_pll_bits(rate, *prate, &mul, &div1, &div2);
614 round_rate = WM8650_BITS_TO_FREQ(*prate, mu
131 vt8500_dclk_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) argument
597 vtwm_pll_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) argument
[all...] |
| /linux-master/drivers/clk/axs10x/ |
| H A D | i2s_pll_clock.c | 86 static const struct i2s_pll_cfg *i2s_pll_get_cfg(unsigned long prate) argument
88 switch (prate) {
112 unsigned long *prate)
115 const struct i2s_pll_cfg *pll_cfg = i2s_pll_get_cfg(*prate);
119 dev_err(clk->dev, "invalid parent rate=%ld\n", *prate);
111 i2s_pll_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) argument
|
| /linux-master/drivers/clk/zynqmp/ |
| H A D | divider.c | 117 * @prate: rate of parent clock
123 unsigned long *prate)
148 return DIV_ROUND_UP_ULL((u64)*prate, bestdiv);
153 rate = divider_round_rate(hw, rate, prate, NULL, width, divider->flags);
155 if (divider->is_frac && (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) && (rate % *prate))
156 *prate = rate;
121 zynqmp_clk_divider_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) argument
|
| /linux-master/drivers/clk/tegra/ |
| H A D | clk-divider.c | 62 unsigned long *prate)
66 unsigned long output_rate = *prate;
73 return *prate;
61 clk_frac_div_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) argument
|
| /linux-master/drivers/clk/zynq/ |
| H A D | pll.c | 48 * @prate: Clock frequency of parent clock
52 unsigned long *prate)
56 fbdiv = DIV_ROUND_CLOSEST(rate, *prate);
62 return *prate * fbdiv;
51 zynq_pll_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) argument
|