clk/renesas/rcar-gen4-cpg.c

85 	unsigned long prate;
87 	prate = req->best_parent_rate * 2;
88 	min_mult = max(div64_ul(req->min_rate, prate), 1ULL);
89 	max_mult = min(div64_ul(req->max_rate, prate), 256ULL);
93 	mult = DIV_ROUND_CLOSEST_ULL(req->rate, prate);
96 	req->rate = prate * mult;
215 	unsigned long rate, prate;
220 		prate = zclk->max_rate;
223 		prate = rate;
226 						  prate * zclk->fixed_div);
228 	prate = req->best_parent_rate / zclk->fixed_div;
229 	min_mult = max(div64_ul(req->min_rate * 32ULL, prate), 1ULL);
230 	max_mult = min(div64_ul(req->max_rate * 32ULL, prate), 32ULL);
234 	mult = DIV_ROUND_CLOSEST_ULL(rate * 32ULL, prate);
237 	req->rate = DIV_ROUND_CLOSEST_ULL((u64)prate * mult, 32);