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02c69593 |
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01-Apr-2021 |
Geert Uytterhoeven <geert+renesas@glider.be> |
clk: renesas: div6: Implement range checking Consider the minimum and maximum clock rates imposed by clock users when calculating the most appropriate clock rate in the .determine_rate() callback. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/35ceb262c71f1b2e9864a39bde9dafd78b2981f4.1617281699.git.geert+renesas@glider.be
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1c924fc6 |
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01-Apr-2021 |
Geert Uytterhoeven <geert+renesas@glider.be> |
clk: renesas: div6: Consider all parents for requested rate Currently the .determine_rate() callback considers only the current parent clock, limiting the range of achievable clock rates on DIV6 clocks with multiple parents, as found on SH/R-Mobile SoCs. Extend the callback to consider all available parent clocks. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/60e639692b462f99e0b6ab868c3675b3d97dbdb0.1617281699.git.geert+renesas@glider.be
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c9d1b58b |
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01-Apr-2021 |
Geert Uytterhoeven <geert+renesas@glider.be> |
clk: renesas: div6: Switch to .determine_rate() As the .round_rate() callback returns a long clock rate, it cannot return clock rates that do not fit in signed long, but do fit in unsigned long. Hence switch the DIV6 clocks on SH/R-Mobile and R-Car SoCs from the old .round_rate() callback to the newer .determine_rate() callback, which does not suffer from this limitation. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/7fd8c45cd8bf5c6d928ca69c8b669be35b93de09.1617281699.git.geert+renesas@glider.be
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23b04c84 |
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01-Apr-2021 |
Geert Uytterhoeven <geert+renesas@glider.be> |
clk: renesas: div6: Simplify src mask handling Simplify the handling of the register bits to select the parent clock, by storing a bitmask instead of separate shift and width values. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/5f05a5110d222ce5a113e683fe2aa726f4100b73.1617281699.git.geert+renesas@glider.be
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6c7bc7db |
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01-Apr-2021 |
Geert Uytterhoeven <geert+renesas@glider.be> |
clk: renesas: div6: Use clamp() instead of clamp_t() As "div" is already "unsigned int", adding "U" suffixes to the constants "1" and "64" allows us to replace the call to clamp_t() by a call to clamp(). This removes hidden casts, and thus helps the compiler doing a better job at type-checking. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/2670c1e3c82a245666578cbbd1fb20d37932fd8e.1617281699.git.geert+renesas@glider.be
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f2fb4fe6 |
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26-Mar-2021 |
Geert Uytterhoeven <geert+renesas@glider.be> |
clk: renesas: Zero init clk_init_data As clk_core_populate_parent_map() checks clk_init_data.num_parents first, and checks clk_init_data.parent_names[] before clk_init_data.parent_data[] and clk_init_data.parent_hws[], leaving the latter uninitialized doesn't do harm for now. However, it is better to play it safe, and initialize all clk_init_data structures to zeroes, to avoid any current and future members containing uninitialized data. Remove a few explicit zero initializers, which are now superfluous. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20210326105434.1574796-1-geert+renesas@glider.be
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ba038611 |
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12-Jun-2019 |
Geert Uytterhoeven <geert+renesas@glider.be> |
clk: renesas: div6: Combine clock-private and parent array allocation Make div6_clock.parents[] a flexible array member, and use the new struct_size() helper, to combine the allocation of the clock-private structure and array of parent clocks. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
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ddbae665 |
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30-Nov-2018 |
Stephen Boyd <sboyd@kernel.org> |
clk: renesas: Remove usage of CLK_IS_BASIC This flag doesn't look to be used by any code, just set in various clk init structures and then never tested again. Remove it from these drivers as it doesn't provide any benefit. Cc: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Cc: <linux-renesas-soc@vger.kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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e848c2ea |
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21-Aug-2018 |
Wolfram Sang <wsa+renesas@sang-engineering.com> |
clk: renesas: use SPDX identifier for Renesas drivers Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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e665f029 |
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28-Aug-2018 |
Rob Herring <robh@kernel.org> |
clk: Convert to using %pOFn instead of device_node.name In preparation to remove the node name pointer from struct device_node, convert printf users to use the %pOFn format specifier. Cc: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: linux-clk@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-renesas-soc@vger.kernel.org Cc: linux-omap@vger.kernel.org Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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c733c7d9 |
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15-Mar-2018 |
Geert Uytterhoeven <geert+renesas@glider.be> |
clk: renesas: div6: Always use readl()/writel() On arm32/arm64, there is no reason to use the (soon deprecated) clk_readl()/clk_writel(). Hence use the generic readl()/writel() instead. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
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9f8c71e5 |
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21-Jun-2017 |
Geert Uytterhoeven <geert+renesas@glider.be> |
clk: renesas: div6: Restore clock state during resume On R-Car Gen3 systems, PSCI system suspend powers down the SoC, losing clock configuration. Register an (optional) notifier to restore the DIV6 clock state during system resume. As DIV6 clocks can be picky w.r.t. modifying multiple register fields at once, restore is not implemented by blindly restoring the register value, but by using the existing cpg_div6_clock_{en,dis}able() helpers. Note that this does not yet support DIV6 clocks with multiple parents, which do not exist on R-Car Gen3 SoCs. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
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2ebedd8d |
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21-Jun-2017 |
Geert Uytterhoeven <geert+renesas@glider.be> |
clk: renesas: div6: Document fields used for parent selection Add the missing documentation for the fields in struct div6_clock related to parent selection for DIV6 clocks with selectable parents, as found in R/SH-Mobile SoCs. Fixes: c6d67fb037f4eaaf ("clk: shmobile: div6: support selectable-input clocks") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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b3a33077 |
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02-Mar-2016 |
Simon Horman <horms+renesas@verge.net.au> |
clk: renesas: move drivers to renesas directory This is part of an ongoing process to migrate from ARCH_SHMOBILE to ARCH_RENESAS the motivation for which being that RENESAS seems to be a more appropriate name than SHMOBILE for the majority of Renesas ARM based SoCs. Along with the above mentioned Kconfig changes it seems appropriate to also rename directories that only hold drivers for such SoCs. Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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