/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
H A D | display_rq_dlg_calc_32.h | 48 const unsigned int pipe_idx); 59 * pipe_idx - index that identifies the e2e_pipe_param that corresponding to this dlg 68 const unsigned int pipe_idx);
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H A D | display_rq_dlg_calc_32.c | 47 const unsigned int pipe_idx) 49 const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src; 74 dml_print("DML_DLG::%s: Calculation for pipe[%d] start, num_pipes=%d\n", __func__, pipe_idx, num_pipes); 85 dpte_group_bytes = get_dpte_group_size_in_bytes(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA 86 mpte_group_bytes = get_vm_group_size_in_bytes(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA 129 detile_buf_size_in_bytes = get_det_buffer_size_kbytes(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * 1024; 132 pipe_idx); 141 num_pipes, pipe_idx); 149 rq_regs->rq_regs_l.swath_height = dml_log2(get_swath_height_l(mode_lib, e2e_pipe_param, num_pipes, pipe_idx)); 150 rq_regs->rq_regs_c.swath_height = dml_log2(get_swath_height_c(mode_lib, e2e_pipe_param, num_pipes, pipe_idx)); 43 dml32_rq_dlg_get_rq_reg(display_rq_regs_st *rq_regs, struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *e2e_pipe_param, const unsigned int num_pipes, const unsigned int pipe_idx) argument 206 dml32_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib, display_dlg_regs_st *dlg_regs, display_ttu_regs_st *ttu_regs, display_e2e_pipe_params_st *e2e_pipe_param, const unsigned int num_pipes, const unsigned int pipe_idx) argument [all...] |
H A D | dcn32_fpu.c | 335 uint32_t i, pipe_idx; local 339 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 346 pipes[pipe_idx].pipe.dest.vstartup_start = 347 get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); 348 pipes[pipe_idx].pipe.dest.vupdate_offset = 349 get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); 350 pipes[pipe_idx].pipe.dest.vupdate_width = 351 get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); 352 pipes[pipe_idx].pipe.dest.vready_offset = 353 get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); 471 unsigned int i, pipe_idx; local 600 unsigned int i, pipe_idx; local 1037 uint32_t i, pipe_idx; local 1644 int i, pipe_idx, active_hubp_count = 0; local 1853 int pipe_idx = sec_pipe->pipe_idx; local 1944 int pipe_cnt, i, pipe_idx; local 2272 int i, pipe_idx, vlevel_temp = 0; local 3469 unsigned int i, pipe_idx; local 3505 unsigned int i, pipe_idx; local [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/dml2/ |
H A D | dml_display_rq_dlg_calc.h | 45 const dml_uint_t pipe_idx); 54 // pipe_idx - index that identifies the e2e_pipe_param that corresponding to this dlg 58 const dml_uint_t pipe_idx);
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H A D | dml_display_rq_dlg_calc.c | 41 const dml_uint_t pipe_idx) 43 dml_uint_t plane_idx = dml_get_plane_idx(mode_lib, pipe_idx); 71 dml_print("DML_DLG::%s: Calculation for pipe[%d] start\n", __func__, pipe_idx); 84 dpte_group_bytes = (dml_uint_t)(dml_get_dpte_group_size_in_bytes(mode_lib, pipe_idx)); 85 mpte_group_bytes = (dml_uint_t)(dml_get_vm_group_size_in_bytes(mode_lib, pipe_idx)); 128 detile_buf_size_in_bytes = (dml_uint_t)(dml_get_det_buffer_size_kbytes(mode_lib, pipe_idx) * 1024); 130 pte_row_height_linear = (dml_uint_t)(dml_get_dpte_row_height_linear_l(mode_lib, pipe_idx)); 138 dml_uint_t p1_pte_row_height_linear = (dml_uint_t)(dml_get_dpte_row_height_linear_c(mode_lib, pipe_idx)); 145 rq_regs->rq_regs_l.swath_height = (dml_uint_t)(dml_log2((dml_float_t) dml_get_swath_height_l(mode_lib, pipe_idx))); 146 rq_regs->rq_regs_c.swath_height = (dml_uint_t)(dml_log2((dml_float_t) dml_get_swath_height_c(mode_lib, pipe_idx))); 39 dml_rq_dlg_get_rq_reg(dml_display_rq_regs_st *rq_regs, struct display_mode_lib_st *mode_lib, const dml_uint_t pipe_idx) argument 197 dml_rq_dlg_get_dlg_reg(dml_display_dlg_regs_st *disp_dlg_regs, dml_display_ttu_regs_st *disp_ttu_regs, struct display_mode_lib_st *mode_lib, const dml_uint_t pipe_idx) argument [all...] |
H A D | dml2_dc_resource_mgmt.c | 130 ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_index[state->res_ctx.pipe_ctx[i].pipe_idx], &plane_id_assigned_to_pipe)) { 153 ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_index[pipe->pipe_idx], 161 pipes[num_found++] = mpc_pipe->pipe_idx; 303 static bool is_pipe_in_candidate_array(const unsigned int pipe_idx, argument 310 if (candidate_array[i] == pipe_idx) 345 // TODO: This doens't make sense really, pipe_idx should always be valid 346 pipe->pipe_idx = preferred_pipe_candidates[i]; 347 assigned_pipes[(*assigned_pipe_count)++] = pipe->pipe_idx; 361 // TODO: This doens't make sense really, pipe_idx should always be valid 362 pipe->pipe_idx 680 is_pipe_used(const struct dc_plane_pipe_pool *pool, unsigned int pipe_idx) argument [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
H A D | display_rq_dlg_calc_20v2.h | 57 // pipe_idx - index that identifies the e2e_pipe_param that corresponding to this dlg 66 const unsigned int pipe_idx,
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H A D | display_rq_dlg_calc_20.h | 57 // pipe_idx - index that identifies the e2e_pipe_param that corresponding to this dlg 66 const unsigned int pipe_idx,
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H A D | display_rq_dlg_calc_20v2.c | 49 const unsigned int pipe_idx, 787 const unsigned int pipe_idx, 795 const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src; 796 const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest; 797 const display_output_params_st *dout = &e2e_pipe_param[pipe_idx].dout; 798 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; 799 const scaler_ratio_depth_st *scl = &e2e_pipe_param[pipe_idx].pipe.scale_ratio_depth; 800 const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps; 940 min_ttu_vblank = get_min_ttu_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); 1029 double dsc_delay = get_dsc_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); 784 dml20v2_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *e2e_pipe_param, const unsigned int num_pipes, const unsigned int pipe_idx, display_dlg_regs_st *disp_dlg_regs, display_ttu_regs_st *disp_ttu_regs, const display_rq_dlg_params_st *rq_dlg_param, const display_dlg_sys_params_st *dlg_sys_param, const bool cstate_en, const bool pstate_en) argument 1550 dml20v2_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib, display_dlg_regs_st *dlg_regs, display_ttu_regs_st *ttu_regs, const display_e2e_pipe_params_st *e2e_pipe_param, const unsigned int num_pipes, const unsigned int pipe_idx, const bool cstate_en, const bool pstate_en, const bool vm_en, const bool ignore_viewport_pos, const bool immediate_flip_support) argument [all...] |
H A D | display_rq_dlg_calc_20.c | 49 const unsigned int pipe_idx, 787 const unsigned int pipe_idx, 795 const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src; 796 const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest; 797 const display_output_params_st *dout = &e2e_pipe_param[pipe_idx].dout; 798 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; 799 const scaler_ratio_depth_st *scl = &e2e_pipe_param[pipe_idx].pipe.scale_ratio_depth; 800 const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps; 940 min_ttu_vblank = get_min_ttu_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); 1028 double dsc_delay = get_dsc_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); 784 dml20_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *e2e_pipe_param, const unsigned int num_pipes, const unsigned int pipe_idx, display_dlg_regs_st *disp_dlg_regs, display_ttu_regs_st *disp_ttu_regs, const display_rq_dlg_params_st *rq_dlg_param, const display_dlg_sys_params_st *dlg_sys_param, const bool cstate_en, const bool pstate_en) argument 1549 dml20_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib, display_dlg_regs_st *dlg_regs, display_ttu_regs_st *ttu_regs, const display_e2e_pipe_params_st *e2e_pipe_param, const unsigned int num_pipes, const unsigned int pipe_idx, const bool cstate_en, const bool pstate_en, const bool vm_en, const bool ignore_viewport_pos, const bool immediate_flip_support) argument [all...] |
H A D | dcn20_fpu.h | 72 int pipe_idx,
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/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
H A D | display_rq_dlg_calc_30.h | 54 // pipe_idx - index that identifies the e2e_pipe_param that corresponding to this dlg 62 const unsigned int pipe_idx,
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H A D | display_rq_dlg_calc_30.c | 893 const unsigned int pipe_idx, 904 const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src; 905 const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest; 906 const display_output_params_st *dout = &e2e_pipe_param[pipe_idx].dout; 907 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; 908 const scaler_ratio_depth_st *scl = &e2e_pipe_param[pipe_idx].pipe.scale_ratio_depth; 909 const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps; 1051 min_ttu_vblank = get_min_ttu_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); 1126 double dsc_delay = get_dsc_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); 1172 dst_x_after_scaler = get_dst_x_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); 890 dml_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *e2e_pipe_param, const unsigned int num_pipes, const unsigned int pipe_idx, display_dlg_regs_st *disp_dlg_regs, display_ttu_regs_st *disp_ttu_regs, const display_rq_dlg_params_st rq_dlg_param, const display_dlg_sys_params_st dlg_sys_param, const bool cstate_en, const bool pstate_en, const bool vm_en, const bool ignore_viewport_pos, const bool immediate_flip_support) argument 1742 dml30_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib, display_dlg_regs_st *dlg_regs, display_ttu_regs_st *ttu_regs, const display_e2e_pipe_params_st *e2e_pipe_param, const unsigned int num_pipes, const unsigned int pipe_idx, const bool cstate_en, const bool pstate_en, const bool vm_en, const bool ignore_viewport_pos, const bool immediate_flip_support) argument [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn21/ |
H A D | display_rq_dlg_calc_21.h | 57 // pipe_idx - index that identifies the e2e_pipe_param that corresponding to this dlg 66 const unsigned int pipe_idx,
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H A D | display_rq_dlg_calc_21.c | 833 const unsigned int pipe_idx, 841 const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src; 842 const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest; 843 const display_output_params_st *dout = &e2e_pipe_param[pipe_idx].dout; 844 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; 845 const scaler_ratio_depth_st *scl = &e2e_pipe_param[pipe_idx].pipe.scale_ratio_depth; 846 const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps; 986 min_ttu_vblank = get_min_ttu_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); 1068 double dsc_delay = get_dsc_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); 1117 dst_x_after_scaler = get_dst_x_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); 829 dml_rq_dlg_get_dlg_params( struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *e2e_pipe_param, const unsigned int num_pipes, const unsigned int pipe_idx, display_dlg_regs_st *disp_dlg_regs, display_ttu_regs_st *disp_ttu_regs, const display_rq_dlg_params_st *rq_dlg_param, const display_dlg_sys_params_st *dlg_sys_param, const bool cstate_en, const bool pstate_en) argument 1657 dml21_rq_dlg_get_dlg_reg( struct display_mode_lib *mode_lib, display_dlg_regs_st *dlg_regs, display_ttu_regs_st *ttu_regs, const display_e2e_pipe_params_st *e2e_pipe_param, const unsigned int num_pipes, const unsigned int pipe_idx, const bool cstate_en, const bool pstate_en, const bool vm_en, const bool ignore_viewport_pos, const bool immediate_flip_support) argument [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
H A D | display_rq_dlg_calc_31.h | 54 // pipe_idx - index that identifies the e2e_pipe_param that corresponding to this dlg 62 const unsigned int pipe_idx,
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H A D | display_rq_dlg_calc_31.c | 856 const unsigned int pipe_idx, 867 const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src; 868 const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest; 869 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; 870 const scaler_ratio_depth_st *scl = &e2e_pipe_param[pipe_idx].pipe.scale_ratio_depth; 871 const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps; 958 int unsigned vba__min_dst_y_next_start = get_min_dst_y_next_start(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // FROM VBA 959 int unsigned vba__vready_after_vcount0 = get_vready_at_or_after_vsync(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA 961 float vba__refcyc_per_line_delivery_pre_l = get_refcyc_per_line_delivery_pre_l_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA 962 float vba__refcyc_per_line_delivery_l = get_refcyc_per_line_delivery_l_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mh 852 dml_rq_dlg_get_dlg_params( struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *e2e_pipe_param, const unsigned int num_pipes, const unsigned int pipe_idx, display_dlg_regs_st *disp_dlg_regs, display_ttu_regs_st *disp_ttu_regs, const display_rq_dlg_params_st *rq_dlg_param, const display_dlg_sys_params_st *dlg_sys_param, const bool cstate_en, const bool pstate_en, const bool vm_en, const bool ignore_viewport_pos, const bool immediate_flip_support) argument 1560 dml31_rq_dlg_get_dlg_reg( struct display_mode_lib *mode_lib, display_dlg_regs_st *dlg_regs, display_ttu_regs_st *ttu_regs, const display_e2e_pipe_params_st *e2e_pipe_param, const unsigned int num_pipes, const unsigned int pipe_idx, const bool cstate_en, const bool pstate_en, const bool vm_en, const bool ignore_viewport_pos, const bool immediate_flip_support) argument [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn314/ |
H A D | display_rq_dlg_calc_314.h | 55 // pipe_idx - index that identifies the e2e_pipe_param that corresponding to this dlg 63 const unsigned int pipe_idx,
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H A D | display_rq_dlg_calc_314.c | 941 const unsigned int pipe_idx, 952 const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src; 953 const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest; 954 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; 955 const scaler_ratio_depth_st *scl = &e2e_pipe_param[pipe_idx].pipe.scale_ratio_depth; 956 const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps; 1043 unsigned int vba__min_dst_y_next_start = get_min_dst_y_next_start(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // FROM VBA 1044 unsigned int vba__vready_after_vcount0 = get_vready_at_or_after_vsync(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA 1046 float vba__refcyc_per_line_delivery_pre_l = get_refcyc_per_line_delivery_pre_l_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA 1047 float vba__refcyc_per_line_delivery_l = get_refcyc_per_line_delivery_l_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mh 937 dml_rq_dlg_get_dlg_params( struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *e2e_pipe_param, const unsigned int num_pipes, const unsigned int pipe_idx, display_dlg_regs_st *disp_dlg_regs, display_ttu_regs_st *disp_ttu_regs, const display_rq_dlg_params_st *rq_dlg_param, const display_dlg_sys_params_st *dlg_sys_param, const bool cstate_en, const bool pstate_en, const bool vm_en, const bool ignore_viewport_pos, const bool immediate_flip_support) argument 1648 dml314_rq_dlg_get_dlg_reg( struct display_mode_lib *mode_lib, display_dlg_regs_st *dlg_regs, display_ttu_regs_st *ttu_regs, const display_e2e_pipe_params_st *e2e_pipe_param, const unsigned int num_pipes, const unsigned int pipe_idx, const bool cstate_en, const bool pstate_en, const bool vm_en, const bool ignore_viewport_pos, const bool immediate_flip_support) argument [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/dml/ |
H A D | display_mode_lib.h | 57 const unsigned int pipe_idx, 75 const unsigned int pipe_idx); 80 const unsigned int pipe_idx);
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/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn301/ |
H A D | dcn301_fpu.c | 418 int i, pipe_idx; local 453 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 457 pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt); 458 pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); 461 pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz; 462 pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz; 464 if (dc->debug.min_disp_clk_khz > pipes[pipe_idx].clks_cfg.dispclk_mhz * 1000) 465 pipes[pipe_idx].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0; 466 if (dc->debug.min_dpp_clk_khz > pipes[pipe_idx] [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/ |
H A D | dc_trace.h | 30 trace_amdgpu_dm_dc_pipe_state(pipe_ctx->pipe_idx, pipe_ctx->plane_state, \
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/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn20/ |
H A D | dcn20_resource.c | 1315 int pipe_idx) 1319 struct display_stream_compressor *dsc_old = dc->current_state->res_ctx.pipe_ctx[pipe_idx].stream_res.dsc; 1326 *dsc = pool->dscs[pipe_idx]; 1327 res_ctx->is_dsc_acquired[pipe_idx] = true; 1471 int pipe_idx = next_odm_pipe->pipe_idx; local 1476 next_odm_pipe->pipe_idx = pipe_idx; 1477 next_odm_pipe->plane_res.mi = pool->mis[next_odm_pipe->pipe_idx]; 1478 next_odm_pipe->plane_res.hubp = pool->hubps[next_odm_pipe->pipe_idx]; 1312 dcn20_acquire_dsc(const struct dc *dc, struct resource_context *res_ctx, struct display_stream_compressor **dsc, int pipe_idx) argument 1555 int pipe_idx = secondary_pipe->pipe_idx; local 1840 int i, pipe_idx, vlevel_split; local 2032 int pipe_cnt, i, pipe_idx, vlevel; local [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/dce60/ |
H A D | dce60_hw_sequencer.c | 52 uint32_t *pipe_idx) 79 if (pipe_ctx->pipe_idx != underlay_idx) { 80 *pipe_idx = i; 118 uint32_t pipe_idx = 0; local 120 if (dce60_should_enable_fbc(dc, context, &pipe_idx)) { 124 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx]; 349 pipe_ctx->pipe_idx, 370 pipe_ctx->pipe_idx, 50 dce60_should_enable_fbc(struct dc *dc, struct dc_state *context, uint32_t *pipe_idx) argument
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/linux-master/drivers/gpu/drm/amd/display/dc/core/ |
H A D | dc_resource.c | 1598 pipe_ctx->pipe_idx, 1682 int preferred_pipe_idx = (pool->pipe_count - 1) - primary_pipe->pipe_idx; 1685 secondary_pipe->pipe_idx = preferred_pipe_idx; 1697 secondary_pipe->pipe_idx = i; 1715 new_pipe = &new_res_ctx->pipe_ctx[cur_sec_opp_head->pipe_idx]; 1717 free_pipe_idx = cur_sec_opp_head->pipe_idx; 1740 new_pipe = &new_res_ctx->pipe_ctx[cur_sec_dpp->pipe_idx]; 1742 free_pipe_idx = cur_sec_dpp->pipe_idx; 1877 struct pipe_ctx *opp_head = &res_ctx->pipe_ctx[otg_master->pipe_idx]; 1896 struct pipe_ctx *pipe = &res_ctx->pipe_ctx[opp_head->pipe_idx]; 2589 int pipe_idx = acquire_first_split_pipe( local 3362 int pipe_idx; local 3419 int pipe_idx = -1; local 4773 reset_sync_context_for_pipe(const struct dc *dc, struct dc_state *context, uint8_t pipe_idx) argument 4896 int pipe_idx = sec_pipe->pipe_idx; local [all...] |