1246149Ssjg/* 2246149Ssjg * Copyright 2017 Advanced Micro Devices, Inc. 3246149Ssjg * 4246149Ssjg * Permission is hereby granted, free of charge, to any person obtaining a 5246149Ssjg * copy of this software and associated documentation files (the "Software"), 6246149Ssjg * to deal in the Software without restriction, including without limitation 7246149Ssjg * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8246149Ssjg * and/or sell copies of the Software, and to permit persons to whom the 9246149Ssjg * Software is furnished to do so, subject to the following conditions: 10246149Ssjg * 11246149Ssjg * The above copyright notice and this permission notice shall be included in 12246149Ssjg * all copies or substantial portions of the Software. 13246149Ssjg * 14246149Ssjg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15246149Ssjg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16246149Ssjg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17246149Ssjg * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18246149Ssjg * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19246149Ssjg * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20246149Ssjg * OTHER DEALINGS IN THE SOFTWARE. 21246149Ssjg * 22246149Ssjg * Authors: AMD 23246149Ssjg * 24246149Ssjg */ 25246149Ssjg 26246149Ssjg#ifndef __DML31_DISPLAY_RQ_DLG_CALC_H__ 27246149Ssjg#define __DML31_DISPLAY_RQ_DLG_CALC_H__ 28246149Ssjg 29246149Ssjg#include "../display_rq_dlg_helpers.h" 30246149Ssjg 31246149Ssjgstruct display_mode_lib; 32246149Ssjg 33246149Ssjg// Function: dml_rq_dlg_get_rq_reg 34246149Ssjg// Main entry point for test to get the register values out of this DML class. 35246149Ssjg// This function calls <get_rq_param> and <extract_rq_regs> fucntions to calculate 36246149Ssjg// and then populate the rq_regs struct 37246149Ssjg// Input: 38246149Ssjg// pipe_param - pipe source configuration (e.g. vp, pitch, scaling, dest, etc.) 39246149Ssjg// Output: 40246149Ssjg// rq_regs - struct that holds all the RQ registers field value. 41246149Ssjg// See also: <display_rq_regs_st> 42246149Ssjgvoid dml31_rq_dlg_get_rq_reg(struct display_mode_lib *mode_lib, 43246149Ssjg display_rq_regs_st *rq_regs, 44246149Ssjg const display_pipe_params_st *pipe_param); 45246149Ssjg 46246149Ssjg// Function: dml_rq_dlg_get_dlg_reg 47246149Ssjg// Calculate and return DLG and TTU register struct given the system setting 48246149Ssjg// Output: 49246149Ssjg// dlg_regs - output DLG register struct 50246149Ssjg// ttu_regs - output DLG TTU register struct 51246149Ssjg// Input: 52246149Ssjg// e2e_pipe_param - "compacted" array of e2e pipe param struct 53246149Ssjg// num_pipes - num of active "pipe" or "route" 54246149Ssjg// pipe_idx - index that identifies the e2e_pipe_param that corresponding to this dlg 55246149Ssjg// cstate - 0: when calculate min_ttu_vblank it is assumed cstate is not required. 1: Normal mode, cstate is considered. 56246149Ssjg// Added for legacy or unrealistic timing tests. 57246149Ssjgvoid dml31_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib, 58246149Ssjg display_dlg_regs_st *dlg_regs, 59246149Ssjg display_ttu_regs_st *ttu_regs, 60246149Ssjg const display_e2e_pipe_params_st *e2e_pipe_param, 61246149Ssjg const unsigned int num_pipes, 62246149Ssjg const unsigned int pipe_idx, 63246149Ssjg const bool cstate_en, 64 const bool pstate_en, 65 const bool vm_en, 66 const bool ignore_viewport_pos, 67 const bool immediate_flip_support); 68 69#endif 70