Searched refs:pipe_count (Results 1 - 25 of 72) sorted by relevance

123

/linux-master/drivers/gpu/drm/amd/display/dc/dcn32/
H A Ddcn32_resource_helpers.c129 for (i = 0; i < dc->res_pool->pipe_count; i++) {
174 for (i = 0; i < dc->res_pool->pipe_count; i++) {
191 for (i = 0; i < dc->res_pool->pipe_count; i++) {
216 for (i = 0; i < dc->res_pool->pipe_count; i++) {
275 for (i = 0; i < dc->res_pool->pipe_count; i++) {
290 for (i = 0; i < dc->res_pool->pipe_count; i++) {
354 for (j = 0; j < dc->res_pool->pipe_count; j++) {
365 for (k = 0; k < dc->res_pool->pipe_count; k++) {
374 for (k = 0; k < dc->res_pool->pipe_count; k++) {
385 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count;
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/linux-master/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_hw_sequencer_debug.c134 for (i = 0; i < pool->pipe_count; i++) {
204 for (i = 0; i < pool->pipe_count; i++) {
249 for (i = 0; i < pool->pipe_count; i++) {
303 for (i = 0; i < pool->pipe_count; i++) {
342 for (i = 0; i < pool->pipe_count; i++) {
395 for (i = 0; i < pool->pipe_count; i++) {
510 for (i = 0; i < pool->pipe_count; i++) {
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn20/
H A Ddcn20_resource.c1108 for (i = 0; i < pool->base.pipe_count; i++) {
1371 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1621 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1666 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1736 for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) {
1759 for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) {
1781 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1810 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1853 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1873 if (plane_count > dc->res_pool->pipe_count /
2254 uint32_t pipe_count = pool->res_cap->num_dwb; local
2277 uint32_t pipe_count = pool->res_cap->num_dwb; local
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/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn32/
H A Ddcn32_hwseq.c230 for (i = 0; i < dc->res_pool->pipe_count; i++) {
349 for (i = 0; i < dc->res_pool->pipe_count; i++) {
380 for (i = 0; i < dc->res_pool->pipe_count; i++) {
401 for (i = 0; i < dc->res_pool->pipe_count; i++) {
603 for (i = 0; i < dc->res_pool->pipe_count; i++) {
618 for (i = 0; i < dc->res_pool->pipe_count; i++) {
642 for (i = 0; i < dc->res_pool->pipe_count; i++) {
702 for (i = 0; i < dc->res_pool->pipe_count; i++) {
917 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1187 for (i = 0; i < dc->res_pool->pipe_count;
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/linux-master/drivers/gpu/drm/amd/display/dc/dcn35/
H A Ddcn35_pg_cntl.c411 for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) {
443 for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) {
486 for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) {
496 for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) {
/linux-master/drivers/gpu/drm/amd/display/dc/core/
H A Ddc.c1094 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1146 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1251 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1396 full_pipe_count = dc->res_pool->pipe_count;
1490 int pipe_count = dc->res_pool->pipe_count; local
1493 for (i = 0; i < pipe_count; i++) {
1516 int pipe_count = dc->res_pool->pipe_count; local
1519 for (i = 0; i < pipe_count;
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H A Ddc_surface.c152 for (i = 0; i < dc->res_pool->pipe_count; i++) {
166 for (i = 0; i < dc->res_pool->pipe_count; i++) {
H A Ddc_debug.c320 for (i = 0; i < dc->res_pool->pipe_count; i++) {
332 for (i = 0; i < dc->res_pool->pipe_count; i++) {
/linux-master/drivers/gpu/drm/amd/display/dc/dce60/
H A Ddce60_resource.c801 for (i = 0; i < pool->base.pipe_count; i++) {
874 for (i = 0; i < dc->res_pool->pipe_count; i++) {
960 pool->base.pipe_count = res_cap.num_timing_generator;
1035 for (i = 0; i < pool->base.pipe_count; i++) {
1097 dc->caps.max_planes = pool->base.pipe_count;
1155 pool->base.pipe_count = res_cap_61.num_timing_generator;
1233 for (i = 0; i < pool->base.pipe_count; i++) {
1295 dc->caps.max_planes = pool->base.pipe_count;
1353 pool->base.pipe_count = res_cap_64.num_timing_generator;
1427 for (i = 0; i < pool->base.pipe_count;
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H A Ddce60_hw_sequencer.c70 for (i = 0; i < dc->res_pool->pipe_count; i++) {
86 if (i == dc->res_pool->pipe_count)
395 for (i = 0; i < dc->res_pool->pipe_count; i++) {
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dce110/
H A Ddce110_resource.c816 for (i = 0; i < pool->base.pipe_count; i++) {
979 dc->res_pool->pipe_count,
1269 pool->opps[pool->pipe_count] = &dce110_oppv->base;
1270 pool->timing_generators[pool->pipe_count] = &dce110_tgv->base;
1271 pool->mis[pool->pipe_count] = &dce110_miv->base;
1272 pool->transforms[pool->pipe_count] = &dce110_xfmv->base;
1273 pool->pipe_count++;
1367 pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1368 pool->base.underlay_pipe_index = pool->base.pipe_count;
1443 for (i = 0; i < pool->base.pipe_count;
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/linux-master/drivers/gpu/drm/amd/display/dc/resource/dce80/
H A Ddce80_resource.c808 for (i = 0; i < pool->base.pipe_count; i++) {
881 for (i = 0; i < dc->res_pool->pipe_count; i++) {
967 pool->base.pipe_count = res_cap.num_timing_generator;
1049 for (i = 0; i < pool->base.pipe_count; i++) {
1111 dc->caps.max_planes = pool->base.pipe_count;
1169 pool->base.pipe_count = res_cap_81.num_timing_generator;
1249 for (i = 0; i < pool->base.pipe_count; i++) {
1311 dc->caps.max_planes = pool->base.pipe_count;
1369 pool->base.pipe_count = res_cap_83.num_timing_generator;
1446 for (i = 0; i < pool->base.pipe_count;
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/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn302/
H A Ddcn302_resource.c711 uint32_t pipe_count = pool->res_cap->num_dwb; local
713 for (i = 0; i < pipe_count; i++) {
746 uint32_t pipe_count = pool->res_cap->num_dwb; local
748 for (i = 0; i < pipe_count; i++) {
966 loaded_ip->max_num_otg = pool->pipe_count;
967 loaded_ip->max_num_dpp = pool->pipe_count;
1022 for (i = 0; i < pool->pipe_count; i++) {
1097 for (i = 0; i < pool->pipe_count; i++) {
1217 pool->pipe_count = pool->res_cap->num_timing_generator;
1370 for (i = 0; i < pool->pipe_count;
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/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn303/
H A Ddcn303_resource.c672 uint32_t pipe_count = pool->res_cap->num_dwb; local
674 for (i = 0; i < pipe_count; i++) {
707 uint32_t pipe_count = pool->res_cap->num_dwb; local
709 for (i = 0; i < pipe_count; i++) {
911 loaded_ip->max_num_otg = pool->pipe_count;
912 loaded_ip->max_num_dpp = pool->pipe_count;
966 for (i = 0; i < pool->pipe_count; i++) {
1041 for (i = 0; i < pool->pipe_count; i++) {
1158 pool->pipe_count = pool->res_cap->num_timing_generator;
1300 for (i = 0; i < pool->pipe_count;
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/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn30/
H A Ddcn30_resource.c1098 for (i = 0; i < pool->base.pipe_count; i++) {
1179 for (i = 0; i < pool->base.pipe_count; i++) {
1219 uint32_t pipe_count = pool->res_cap->num_dwb; local
1221 for (i = 0; i < pipe_count; i++) {
1244 uint32_t pipe_count = pool->res_cap->num_dwb; local
1246 for (i = 0; i < pipe_count; i++) {
1332 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1387 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1514 loaded_ip->max_num_dpp = pool->base.pipe_count;
1600 for (i = dc->res_pool->pipe_count
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/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn314/
H A Ddcn314_fpu.c196 dcn3_14_ip.max_num_dpp = dc->res_pool->pipe_count;
321 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
412 for (i = 0; i < dc->res_pool->pipe_count; i++) {
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn10/
H A Ddcn10_hwseq.c106 for (i = 0; i < dc->res_pool->pipe_count; i++) {
180 for (i = 0; i < pool->pipe_count; i++) {
212 for (i = 0; i < pool->pipe_count; i++) {
237 for (i = 0; i < pool->pipe_count; i++) {
269 for (i = 0; i < pool->pipe_count; i++) {
298 for (i = 0; i < pool->pipe_count; i++) {
370 for (i = 0; i < pool->pipe_count; i++) {
842 for (i = 0; i < dc->res_pool->pipe_count; i++) {
886 for (i = 0; i < dc->res_pool->pipe_count; i++) {
913 for (i = 0; i < dc->res_pool->pipe_count;
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/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn35/
H A Ddcn35_fpu.c241 dcn3_5_ip.max_num_dpp = dc->res_pool->pipe_count;
449 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
554 for (i = 0; i < dc->res_pool->pipe_count; i++) {
581 for (i = 0; i < dc->res_pool->pipe_count; i++) {
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn351/
H A Ddcn351_fpu.c276 dcn3_51_ip.max_num_dpp = dc->res_pool->pipe_count;
484 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
589 for (i = 0; i < dc->res_pool->pipe_count; i++) {
616 for (i = 0; i < dc->res_pool->pipe_count; i++) {
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn315/
H A Ddcn315_resource.c1396 for (i = 0; i < pool->base.pipe_count; i++) {
1511 uint32_t pipe_count = pool->res_cap->num_dwb; local
1513 for (i = 0; i < pipe_count; i++) {
1536 uint32_t pipe_count = pool->res_cap->num_dwb; local
1538 for (i = 0; i < pipe_count; i++) {
1640 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1675 for (i = 0, pipe_cnt = 0, crb_pipes = 0; i < dc->res_pool->pipe_count; i++) {
1741 for (i = 0, pipe_cnt = 0, crb_idx = 0; i < dc->res_pool->pipe_count; i++) {
1858 pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
2002 for (i = 0; i < pool->base.pipe_count;
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/linux-master/sound/pci/mixart/
H A Dmixart_core.h233 u32 pipe_count; /* set to 1 for instance */ member in struct:mixart_group_state_req
234 struct mixart_uid pipe_uid; /* could be an array[pipe_count], in theory */
402 u32 pipe_count; /* set to 1 (array size !) */ member in struct:mixart_stream_param_desc
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn10/
H A Ddcn10_resource.c930 for (i = 0; i < pool->base.pipe_count; i++) {
1345 pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1348 pool->base.pipe_count = 3;
1563 for (i = 0; i < pool->base.pipe_count; i++) {
1632 pool->base.pipe_count = j;
1638 dc->dml.ip.max_num_dpp = pool->base.pipe_count;
1639 dc->dcn_ip->max_num_dpp = pool->base.pipe_count;
1660 dc->caps.max_planes = pool->base.pipe_count;
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn31/
H A Ddcn31_fpu.c527 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
562 for (i = 0; i < dc->res_pool->pipe_count; i++)
566 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
594 dcn3_1_ip.max_num_dpp = dc->res_pool->pipe_count;
666 dcn3_15_ip.max_num_dpp = dc->res_pool->pipe_count;
733 dcn3_16_ip.max_num_dpp = dc->res_pool->pipe_count;
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn20/
H A Ddcn20_hwseq.c87 for (i = 0; i < pool->pipe_count; i++) {
158 for (i = 0; i < pool->pipe_count; i++) {
2009 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2021 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2036 for (i = 0; i < dc->res_pool->pipe_count; i++)
2043 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2064 for (i = 0; i < dc->res_pool->pipe_count; i++)
2072 for (i = 0; i < dc->res_pool->pipe_count; i++)
2091 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2104 for (i = 0; i < dc->res_pool->pipe_count;
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/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn32/
H A Ddcn32_fpu.c339 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
484 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
561 for (i = 0; i < dc->res_pool->pipe_count; i++) {
572 free_pipes = dc->res_pool->pipe_count - num_pipes;
606 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
678 unsigned int min_pipe_split = dc->res_pool->pipe_count + 1; // init as max number of pipes + 1
681 for (i = 0; i < dc->res_pool->pipe_count; i++) {
701 // should not equal to the pipe_count)
702 if (free_pipes >= min_pipe_split && free_pipes < dc->res_pool->pipe_count)
731 for (i = 0; i < dc->res_pool->pipe_count;
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