Searched refs:phy_addr (Results 1 - 25 of 70) sorted by relevance

123

/u-boot/board/freescale/t104xrdb/
H A Deth.c24 int phy_addr = 0; local
48 phy_addr = CFG_SYS_SGMII1_PHY_ADDR;
50 phy_addr = CFG_SYS_SGMII2_PHY_ADDR;
52 phy_addr = CFG_SYS_SGMII3_PHY_ADDR;
53 fm_info_set_phy_address(i, phy_addr);
61 phy_addr = CFG_SYS_RGMII1_PHY_ADDR;
63 phy_addr = CFG_SYS_RGMII2_PHY_ADDR;
64 fm_info_set_phy_address(i, phy_addr);
/u-boot/drivers/net/phy/
H A Dmv88e6352.c34 static int sw_wait_rdy(const char *devname, u8 phy_addr) argument
43 ret = miiphy_read(devname, phy_addr, COMMAND_REG, &command);
58 static int sw_reg_read(const char *devname, u8 phy_addr, u8 port, argument
64 ret = sw_wait_rdy(devname, phy_addr);
71 ret = miiphy_write(devname, phy_addr, COMMAND_REG, command);
75 ret = sw_wait_rdy(devname, phy_addr);
79 ret = miiphy_read(devname, phy_addr, DATA_REG, data);
84 static int sw_reg_write(const char *devname, u8 phy_addr, u8 port, argument
90 ret = sw_wait_rdy(devname, phy_addr);
95 ret = miiphy_write(devname, phy_addr, DATA_RE
113 ppu_enable(const char *devname, u8 phy_addr) argument
143 ppu_disable(const char *devname, u8 phy_addr) argument
173 mv88e_sw_program(const char *devname, u8 phy_addr, struct mv88e_sw_reg *regs, int regs_nb) argument
205 mv88e_sw_reset(const char *devname, u8 phy_addr) argument
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H A Dca_phy.c25 u8 phy_addr; local
29 for (phy_addr = 4; phy_addr > 0; phy_addr--) {
30 phydev->addr = phy_addr;
41 for (phy_addr = 1; phy_addr < 5; phy_addr++) {
43 phydev->addr = phy_addr;
52 printf("%s: phy_addr
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/u-boot/drivers/net/ti/
H A Ddavinci_emac.c63 #define emac_gigabit_enable(phy_addr) davinci_eth_gigabit_enable(phy_addr)
65 #define emac_gigabit_enable(phy_addr) /* no gigabit to enable */
75 static int gen_init_phy(int phy_addr);
76 static int gen_is_phy_connected(int phy_addr);
77 static int gen_get_link_speed(int phy_addr);
78 static int gen_auto_negotiate(int phy_addr);
210 int davinci_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data) argument
220 ((phy_addr & 0x1f) << 16),
236 int davinci_eth_phy_write(u_int8_t phy_addr, u_int8_ argument
257 gen_init_phy(int phy_addr) argument
269 gen_is_phy_connected(int phy_addr) argument
287 gen_get_link_speed(int phy_addr) argument
324 gen_auto_negotiate(int phy_addr) argument
399 davinci_eth_gigabit_enable(int phy_addr) argument
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H A Ddavinci_emac.h293 int davinci_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data);
294 int davinci_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data);
298 int (*init)(int phy_addr);
299 int (*is_phy_connected)(int phy_addr);
300 int (*get_link_speed)(int phy_addr);
301 int (*auto_negotiate)(int phy_addr);
/u-boot/arch/mips/mach-octeon/
H A Dcvmx-helper-board.c340 phy_info->phy_addr = -1;
351 phy_info->phy_addr = -1;
354 if (phy_info->phy_addr == -1) {
357 phy_info->phy_addr = -1;
361 phy_info->phy_addr = -1;
376 if (phy_info->phy_addr < 0)
675 u32 phy_addr = phy_info->phy_addr; local
679 cvmx_mdio_write(phy_addr >> 8, phy_addr
726 u32 phy_addr = phy_info->phy_addr; local
789 u32 phy_addr = phy_info->phy_addr; local
848 u32 phy_addr = phy_info->phy_addr; local
899 u32 phy_addr = phy_info->phy_addr; local
963 int phy_addr; local
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H A Dcvmx-bootmem.c796 int __cvmx_bootmem_phy_free(u64 phy_addr, u64 size, u32 flags) argument
803 CAST_ULL(phy_addr), CAST_ULL(size));
809 if (!size || !phy_addr)
818 if (cur_addr == 0 || phy_addr < cur_addr) {
820 if (cur_addr && phy_addr + size > cur_addr)
822 else if (phy_addr + size == cur_addr) {
824 cvmx_bootmem_phy_set_next(phy_addr,
826 cvmx_bootmem_phy_set_size(phy_addr,
828 CVMX_BOOTMEM_DESC_SET_FIELD(head_addr, phy_addr);
833 cvmx_bootmem_phy_set_next(phy_addr, cur_add
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/u-boot/board/freescale/lx2160a/
H A Deth_lx2160ardb.c70 static int fdt_update_phy_addr(void *fdt, int dpmac_id, int phy_addr) argument
97 phy_addr = cpu_to_fdt32(phy_addr);
98 err = fdt_setprop(fdt, offset, "reg", &phy_addr, sizeof(phy_addr));
/u-boot/drivers/net/pfe_eth/
H A Dpfe_mdio.c19 static int pfe_write_addr(struct mii_dev *bus, int phy_addr, int dev_addr, argument
29 phy = ((phy_addr & EMAC_MII_DATA_PA_MASK) << EMAC_MII_DATA_PA_SHIFT);
53 static int pfe_phy_read(struct mii_dev *bus, int phy_addr, int dev_addr, argument
67 pfe_write_addr(bus, phy_addr, dev_addr, reg_addr);
72 phy = ((phy_addr & EMAC_MII_DATA_PA_MASK) << EMAC_MII_DATA_PA_SHIFT);
103 phy_addr, reg_addr, val);
108 static int pfe_phy_write(struct mii_dev *bus, int phy_addr, int dev_addr, argument
121 pfe_write_addr(bus, phy_addr, dev_addr, reg_addr);
126 phy = ((phy_addr & EMAC_MII_DATA_PA_MASK) << EMAC_MII_DATA_PA_SHIFT);
152 debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phy_addr,
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/u-boot/test/py/tests/
H A Dtest_mdio.py18 "eth0": {"phy_addr": 0xc, "device_name": "TI DP83867", "reg": 0,
20 "eth1": {"phy_addr": 0xa0, "device_name": "TI DP83867", "reg": 1,
38 phy_addr = val.get("phy_addr")
41 assert f"{phy_addr:x} -" in output
50 phy_addr = hex(val.get("phy_addr"))
55 output = u_boot_console.run_command(f"mdio read {phy_addr} {reg}")
56 assert f"PHY at address {int(phy_addr, 16):x}:" in output
65 phy_addr
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/u-boot/drivers/net/octeon/
H A Docteon_mdio.c56 static int octeon_mdio_read(struct udevice *mdio_dev, int phy_addr, argument
63 debug("%s(0x%p(%s): bus_id=%d phy_addr=%d, 0x%x, 0x%x) - ", __func__,
64 dev, dev->name, p->bus_id, phy_addr, dev_addr, reg_addr);
67 value = cvmx_mdio_45_read(p->bus_id & 0xff, phy_addr, dev_addr,
70 value = cvmx_mdio_read(p->bus_id & 0xff, phy_addr, reg_addr);
77 static int octeon_mdio_write(struct udevice *mdio_dev, int phy_addr, argument
83 debug("%s(0x%p(%s): bus_id=%d phy_addr=%d, 0x%x, 0x%x, 0x%x)\n",
84 __func__, dev, dev->name, p->bus_id, phy_addr, dev_addr, reg_addr,
89 return cvmx_mdio_45_write(p->bus_id & 0xff, phy_addr, dev_addr,
93 return cvmx_mdio_write(p->bus_id & 0xff, phy_addr, reg_add
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/u-boot/include/
H A Dmv88e6352.h70 int mv88e_sw_reset(const char *devname, u8 phy_addr);
71 int mv88e_sw_program(const char *devname, u8 phy_addr,
H A Dnetdev.h42 int dnet_eth_initialize(int id, void *regs, unsigned int phy_addr);
57 int macb_eth_initialize(int id, void *regs, unsigned int phy_addr);
62 int phy_addr);
H A Dcpsw.h41 int phy_addr; member in struct:cpsw_slave_data
/u-boot/drivers/net/
H A Dmcfmii.c131 return info->phy_addr;
224 info->phy_addr = mii_discover_phy(info);
226 if (info->phy_addr == -1)
233 miiphy_read(dev->name, info->phy_addr, MII_BMCR, &status);
244 miiphy_read(dev->name, info->phy_addr, MII_BMSR, &status);
254 info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
255 info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
H A Dsni_netsec.c272 u32 phy_addr, freq; member in struct:netsec_priv
451 int phy_addr, int reg_addr)
456 if (phy_addr != 7)
460 phy_addr << NETSEC_GMAC_GAR_REG_SHIFT_PA |
479 int phy_addr, int reg_addr, u16 val)
483 if (phy_addr != 7)
489 phy_addr << NETSEC_GMAC_GAR_REG_SHIFT_PA |
506 netsec_get_phy_reg(priv, phy_addr, MII_PHYSID1);
744 int phy_addr, int devad, int reg_addr)
746 return netsec_get_phy_reg(bus->priv, phy_addr, reg_add
450 netsec_get_phy_reg(struct netsec_priv *priv, int phy_addr, int reg_addr) argument
478 netsec_set_phy_reg(struct netsec_priv *priv, int phy_addr, int reg_addr, u16 val) argument
743 _netsec_get_phy_reg(struct mii_dev *bus, int phy_addr, int devad, int reg_addr) argument
749 _netsec_set_phy_reg(struct mii_dev *bus, int phy_addr, int devad, int reg_addr, u16 val) argument
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H A Dmt7620-eth.c233 int phy_addr; member in struct:mt7620_gsw_port_cfg
563 if (priv->port_cfg[0].phy_addr > 0)
564 mt7620_phy_restart_an(priv, priv->port_cfg[0].phy_addr);
566 if (priv->port_cfg[1].phy_addr > 0)
567 mt7620_phy_restart_an(priv, priv->port_cfg[1].phy_addr);
674 if (priv->port_cfg[0].phy_addr < 0 && priv->port_cfg[1].phy_addr < 0)
677 if (priv->port_cfg[0].phy_addr > 0 && priv->port_cfg[1].phy_addr > 0) {
678 phy_addr_st = priv->port_cfg[0].phy_addr;
1052 u32 phy_addr; local
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H A Dmtk_eth.c144 int phy_addr; member in struct:mtk_eth_priv
474 u8 phy_addr; local
479 phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, phy);
481 return mt7531_mii_rw(priv, phy_addr, reg, 0, MDIO_CMD_READ,
488 u8 phy_addr; local
493 phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, phy);
495 return mt7531_mii_rw(priv, phy_addr, reg, val, MDIO_CMD_WRITE,
502 u8 phy_addr; local
508 phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, addr);
510 ret = mt7531_mii_rw(priv, phy_addr, deva
522 u8 phy_addr; local
609 u8 phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, 0); local
616 u8 phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, 0); local
693 u16 phy_addr, phy_val; local
917 u16 phy_addr, phy_val; local
1030 u16 phy_addr, phy_val; local
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/u-boot/drivers/net/ldpaa_eth/
H A Dldpaa_wriop.c38 dpmac_info[dpmac_id].phy_addr[phy_num] = -1;
51 dpmac_info[dpmac_id].phy_addr[phy_num] = -1;
137 dpmac_info[i].phy_addr[phy_num] = address;
151 return dpmac_info[i].phy_addr[phy_num];
/u-boot/net/
H A Dmdio-uclass.c215 u32 phy_addr; local
217 if (ofnode_read_u32(phynode, "reg", &phy_addr))
230 return phy_find_by_mask(pdata->mii_bus, BIT(phy_addr));
248 u32 phy_addr; local
269 if (ofnode_read_u32(phynode, "reg", &phy_addr)) {
282 phy = dm_mdio_phy_connect(mdiodev, phy_addr, ethdev, interface);
/u-boot/drivers/net/octeontx/
H A Dsmi.c263 int rxaui_phy_xs_init(struct mii_dev *bus, int phy_addr) argument
270 phy_id1 = octeontx_phy_read(bus, phy_addr, 1, 0x2);
271 phy_id2 = octeontx_phy_read(bus, phy_addr, 1, 0x3);
283 reg = octeontx_phy_read(bus, phy_addr, 4, 0x0);
287 octeontx_phy_write(bus, phy_addr, 4, 0x0, reg);
291 reg = octeontx_phy_read(bus, phy_addr, 4, 0x0);
301 octeontx_phy_write(bus, phy_addr, 4, 0xc003, 0x5);
/u-boot/board/compulab/cm_t43/
H A Dcm_t43.c80 .phy_addr = 0,
86 .phy_addr = 1,
/u-boot/drivers/net/mscc_eswitch/
H A Dservalt_switch.c118 size_t phy_addr; member in struct:servalt_phy_port_t
404 size_t phy_addr, struct mii_dev *bus)
406 priv->ports[index].phy_addr = phy_addr;
418 size_t phy_addr; local
456 phy_addr = res.start;
475 add_port_entry(priv, i, phy_addr, bus);
484 phy_connect(priv->ports[i].bus, priv->ports[i].phy_addr, dev,
403 add_port_entry(struct servalt_private *priv, size_t index, size_t phy_addr, struct mii_dev *bus) argument
/u-boot/drivers/phy/marvell/
H A Dcomphy_a3700.c177 reg_set16(phy_addr(PCIE, LANE_CFG1), bf_use_max_pll_rate, 0);
182 reg_set16(phy_addr(PCIE, GLOB_CLK_SRC_LO), bf_cfg_sel_20b, 0);
187 reg_set16(phy_addr(PCIE, MISC_REG1), bf_sel_bits_pcie_force, 0);
192 reg_set16(phy_addr(PCIE, PWR_MGM_TIM1), 0x10C, 0xFFFF);
197 reg_set16(phy_addr(PCIE, UNIT_CTRL), 0x60 | rb_idle_sync_en, 0xFFFF);
202 reg_set16(phy_addr(PCIE, MISC_REG0),
216 reg_set16(phy_addr(PCIE, PWR_PLL_CTRL), 0xFC63, 0xFFFF);
219 reg_set16(phy_addr(PCIE, PWR_PLL_CTRL), 0xFC62, 0xFFFF);
225 reg_set16(phy_addr(PCIE, KVCO_CAL_CTRL), 0x0040 | rb_use_max_pll_rate,
232 reg_set16(phy_addr(PCI
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/u-boot/include/fsl-mc/
H A Dldpaa_wriop.h47 int phy_addr[WRIOP_MAX_PHY_NUM]; member in struct:wriop_dpmac_info

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