Lines Matching refs:phy_addr
178 reg_set16(phy_addr(PCIE, LANE_CFG1), bf_use_max_pll_rate, 0);
183 reg_set16(phy_addr(PCIE, GLOB_CLK_SRC_LO), bf_cfg_sel_20b, 0);
188 reg_set16(phy_addr(PCIE, MISC_REG1), bf_sel_bits_pcie_force, 0);
193 reg_set16(phy_addr(PCIE, PWR_MGM_TIM1), 0x10C, 0xFFFF);
198 reg_set16(phy_addr(PCIE, UNIT_CTRL), 0x60 | rb_idle_sync_en, 0xFFFF);
203 reg_set16(phy_addr(PCIE, MISC_REG0),
217 reg_set16(phy_addr(PCIE, PWR_PLL_CTRL), 0xFC63, 0xFFFF);
220 reg_set16(phy_addr(PCIE, PWR_PLL_CTRL), 0xFC62, 0xFFFF);
226 reg_set16(phy_addr(PCIE, KVCO_CAL_CTRL), 0x0040 | rb_use_max_pll_rate,
233 reg_set16(phy_addr(PCIE, SYNC_PATTERN), phy_txd_inv, 0);
235 reg_set16(phy_addr(PCIE, SYNC_PATTERN), 0, phy_txd_inv);
238 reg_set16(phy_addr(PCIE, SYNC_PATTERN), phy_rxd_inv, 0);
240 reg_set16(phy_addr(PCIE, SYNC_PATTERN), 0, phy_rxd_inv);
245 reg_set16(phy_addr(PCIE, GLOB_PHY_CTRL0),
253 ret = comphy_poll_reg(phy_addr(PCIE, LANE_STAT1), /* address */
368 reg_set16(phy_addr(USB3, reg), data, mask);
513 ret = comphy_poll_reg(phy_addr(USB3, LANE_STAT1), /* address */