1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright (C) 2015 Freescale Semiconductor
4 */
5
6#ifndef __LDPAA_WRIOP_H
7#define __LDPAA_WRIOP_H
8
9#include <phy.h>
10
11#define DEFAULT_WRIOP_MDIO1_NAME "FSL_MDIO0"
12#define DEFAULT_WRIOP_MDIO2_NAME "FSL_MDIO1"
13#define WRIOP_MAX_PHY_NUM        2
14
15enum wriop_port {
16	WRIOP1_DPMAC1 = 1,
17	WRIOP1_DPMAC2,
18	WRIOP1_DPMAC3,
19	WRIOP1_DPMAC4,
20	WRIOP1_DPMAC5,
21	WRIOP1_DPMAC6,
22	WRIOP1_DPMAC7,
23	WRIOP1_DPMAC8,
24	WRIOP1_DPMAC9,
25	WRIOP1_DPMAC10,
26	WRIOP1_DPMAC11,
27	WRIOP1_DPMAC12,
28	WRIOP1_DPMAC13,
29	WRIOP1_DPMAC14,
30	WRIOP1_DPMAC15,
31	WRIOP1_DPMAC16,
32	WRIOP1_DPMAC17,
33	WRIOP1_DPMAC18,
34	WRIOP1_DPMAC19,
35	WRIOP1_DPMAC20,
36	WRIOP1_DPMAC21,
37	WRIOP1_DPMAC22,
38	WRIOP1_DPMAC23,
39	WRIOP1_DPMAC24,
40	NUM_WRIOP_PORTS,
41};
42
43struct wriop_dpmac_info {
44	u8 enabled;
45	u8 id;
46	u8 board_mux;
47	int phy_addr[WRIOP_MAX_PHY_NUM];
48	phy_interface_t enet_if;
49	struct phy_device *phydev[WRIOP_MAX_PHY_NUM];
50	struct mii_dev *bus;
51};
52
53extern struct wriop_dpmac_info dpmac_info[NUM_WRIOP_PORTS];
54
55void wriop_init_dpmac(int sd, int dpmac_id, int lane_prtcl);
56void wriop_init_dpmac_enet_if(int dpmac_id, phy_interface_t enet_if);
57int wriop_disable_dpmac(int dpmac_id);
58int wriop_enable_dpmac(int dpmac_id);
59int wriop_is_enabled_dpmac(int dpmac_id);
60int wriop_set_mdio(int dpmac_id, struct mii_dev *bus);
61struct mii_dev *wriop_get_mdio(int dpmac_id);
62int wriop_set_phy_address(int dpmac_id, int phy_num, int address);
63int wriop_get_phy_address(int dpmac_id, int phy_num);
64int wriop_set_phy_dev(int dpmac_id, int phy_num, struct phy_device *phydev);
65struct phy_device *wriop_get_phy_dev(int dpmac_id, int phy_num);
66phy_interface_t wriop_get_enet_if(int dpmac_id);
67
68void wriop_dpmac_disable(int dpmac_id);
69void wriop_dpmac_enable(int dpmac_id);
70phy_interface_t wriop_dpmac_enet_if(int dpmac_id, int lane_prtcl);
71void wriop_init_dpmac_qsgmii(int sd, int lane_prtcl);
72void wriop_init_rgmii(void);
73#endif	/* __LDPAA_WRIOP_H */
74