1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Copyright (C) 2011 Ilya Yanok, Emcraft Systems 4 * 5 * Based on: mach-davinci/emac_defs.h 6 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> 7 */ 8 9#ifndef _DAVINCI_EMAC_H_ 10#define _DAVINCI_EMAC_H_ 11/* Ethernet Min/Max packet size */ 12#define EMAC_MIN_ETHERNET_PKT_SIZE 60 13#define EMAC_MAX_ETHERNET_PKT_SIZE 1518 14/* Buffer size (should be aligned on 32 byte and cache line) */ 15#define EMAC_RXBUF_SIZE ALIGN(ALIGN(EMAC_MAX_ETHERNET_PKT_SIZE, 32),\ 16 ARCH_DMA_MINALIGN) 17 18/* Number of RX packet buffers 19 * NOTE: Only 1 buffer supported as of now 20 */ 21#define EMAC_MAX_RX_BUFFERS 10 22 23 24/*********************************************** 25 ******** Internally used macros *************** 26 ***********************************************/ 27 28#define EMAC_CH_TX 1 29#define EMAC_CH_RX 0 30 31/* Each descriptor occupies 4 words, lets start RX desc's at 0 and 32 * reserve space for 64 descriptors max 33 */ 34#define EMAC_RX_DESC_BASE 0x0 35#define EMAC_TX_DESC_BASE 0x1000 36 37/* EMAC Teardown value */ 38#define EMAC_TEARDOWN_VALUE 0xfffffffc 39 40/* MII Status Register */ 41#define MII_STATUS_REG 1 42/* PHY Configuration register */ 43#define PHY_CONF_TXCLKEN (1 << 5) 44 45/* Number of statistics registers */ 46#define EMAC_NUM_STATS 36 47 48 49/* EMAC Descriptor */ 50typedef volatile struct _emac_desc 51{ 52 u_int32_t next; /* Pointer to next descriptor 53 in chain */ 54 u_int8_t *buffer; /* Pointer to data buffer */ 55 u_int32_t buff_off_len; /* Buffer Offset(MSW) and Length(LSW) */ 56 u_int32_t pkt_flag_len; /* Packet Flags(MSW) and Length(LSW) */ 57} emac_desc; 58 59/* CPPI bit positions */ 60#define EMAC_CPPI_SOP_BIT (0x80000000) 61#define EMAC_CPPI_EOP_BIT (0x40000000) 62#define EMAC_CPPI_OWNERSHIP_BIT (0x20000000) 63#define EMAC_CPPI_EOQ_BIT (0x10000000) 64#define EMAC_CPPI_TEARDOWN_COMPLETE_BIT (0x08000000) 65#define EMAC_CPPI_PASS_CRC_BIT (0x04000000) 66 67#define EMAC_CPPI_RX_ERROR_FRAME (0x03fc0000) 68 69#define EMAC_MACCONTROL_MIIEN_ENABLE (0x20) 70#define EMAC_MACCONTROL_FULLDUPLEX_ENABLE (0x1) 71#define EMAC_MACCONTROL_GIGABIT_ENABLE (1 << 7) 72#define EMAC_MACCONTROL_GIGFORCE (1 << 17) 73#define EMAC_MACCONTROL_RMIISPEED_100 (1 << 15) 74 75#define EMAC_MAC_ADDR_MATCH (1 << 19) 76#define EMAC_MAC_ADDR_IS_VALID (1 << 20) 77 78#define EMAC_RXMBPENABLE_RXCAFEN_ENABLE (0x200000) 79#define EMAC_RXMBPENABLE_RXBROADEN (0x2000) 80 81 82#define MDIO_CONTROL_IDLE (0x80000000) 83#define MDIO_CONTROL_ENABLE (0x40000000) 84#define MDIO_CONTROL_FAULT_ENABLE (0x40000) 85#define MDIO_CONTROL_FAULT (0x80000) 86#define MDIO_USERACCESS0_GO (0x80000000) 87#define MDIO_USERACCESS0_WRITE_READ (0x0) 88#define MDIO_USERACCESS0_WRITE_WRITE (0x40000000) 89#define MDIO_USERACCESS0_ACK (0x20000000) 90 91/* Ethernet MAC Registers Structure */ 92typedef struct { 93 dv_reg TXIDVER; 94 dv_reg TXCONTROL; 95 dv_reg TXTEARDOWN; 96 u_int8_t RSVD0[4]; 97 dv_reg RXIDVER; 98 dv_reg RXCONTROL; 99 dv_reg RXTEARDOWN; 100 u_int8_t RSVD1[100]; 101 dv_reg TXINTSTATRAW; 102 dv_reg TXINTSTATMASKED; 103 dv_reg TXINTMASKSET; 104 dv_reg TXINTMASKCLEAR; 105 dv_reg MACINVECTOR; 106 u_int8_t RSVD2[12]; 107 dv_reg RXINTSTATRAW; 108 dv_reg RXINTSTATMASKED; 109 dv_reg RXINTMASKSET; 110 dv_reg RXINTMASKCLEAR; 111 dv_reg MACINTSTATRAW; 112 dv_reg MACINTSTATMASKED; 113 dv_reg MACINTMASKSET; 114 dv_reg MACINTMASKCLEAR; 115 u_int8_t RSVD3[64]; 116 dv_reg RXMBPENABLE; 117 dv_reg RXUNICASTSET; 118 dv_reg RXUNICASTCLEAR; 119 dv_reg RXMAXLEN; 120 dv_reg RXBUFFEROFFSET; 121 dv_reg RXFILTERLOWTHRESH; 122 u_int8_t RSVD4[8]; 123 dv_reg RX0FLOWTHRESH; 124 dv_reg RX1FLOWTHRESH; 125 dv_reg RX2FLOWTHRESH; 126 dv_reg RX3FLOWTHRESH; 127 dv_reg RX4FLOWTHRESH; 128 dv_reg RX5FLOWTHRESH; 129 dv_reg RX6FLOWTHRESH; 130 dv_reg RX7FLOWTHRESH; 131 dv_reg RX0FREEBUFFER; 132 dv_reg RX1FREEBUFFER; 133 dv_reg RX2FREEBUFFER; 134 dv_reg RX3FREEBUFFER; 135 dv_reg RX4FREEBUFFER; 136 dv_reg RX5FREEBUFFER; 137 dv_reg RX6FREEBUFFER; 138 dv_reg RX7FREEBUFFER; 139 dv_reg MACCONTROL; 140 dv_reg MACSTATUS; 141 dv_reg EMCONTROL; 142 dv_reg FIFOCONTROL; 143 dv_reg MACCONFIG; 144 dv_reg SOFTRESET; 145 u_int8_t RSVD5[88]; 146 dv_reg MACSRCADDRLO; 147 dv_reg MACSRCADDRHI; 148 dv_reg MACHASH1; 149 dv_reg MACHASH2; 150 dv_reg BOFFTEST; 151 dv_reg TPACETEST; 152 dv_reg RXPAUSE; 153 dv_reg TXPAUSE; 154 u_int8_t RSVD6[16]; 155 dv_reg RXGOODFRAMES; 156 dv_reg RXBCASTFRAMES; 157 dv_reg RXMCASTFRAMES; 158 dv_reg RXPAUSEFRAMES; 159 dv_reg RXCRCERRORS; 160 dv_reg RXALIGNCODEERRORS; 161 dv_reg RXOVERSIZED; 162 dv_reg RXJABBER; 163 dv_reg RXUNDERSIZED; 164 dv_reg RXFRAGMENTS; 165 dv_reg RXFILTERED; 166 dv_reg RXQOSFILTERED; 167 dv_reg RXOCTETS; 168 dv_reg TXGOODFRAMES; 169 dv_reg TXBCASTFRAMES; 170 dv_reg TXMCASTFRAMES; 171 dv_reg TXPAUSEFRAMES; 172 dv_reg TXDEFERRED; 173 dv_reg TXCOLLISION; 174 dv_reg TXSINGLECOLL; 175 dv_reg TXMULTICOLL; 176 dv_reg TXEXCESSIVECOLL; 177 dv_reg TXLATECOLL; 178 dv_reg TXUNDERRUN; 179 dv_reg TXCARRIERSENSE; 180 dv_reg TXOCTETS; 181 dv_reg FRAME64; 182 dv_reg FRAME65T127; 183 dv_reg FRAME128T255; 184 dv_reg FRAME256T511; 185 dv_reg FRAME512T1023; 186 dv_reg FRAME1024TUP; 187 dv_reg NETOCTETS; 188 dv_reg RXSOFOVERRUNS; 189 dv_reg RXMOFOVERRUNS; 190 dv_reg RXDMAOVERRUNS; 191 u_int8_t RSVD7[624]; 192 dv_reg MACADDRLO; 193 dv_reg MACADDRHI; 194 dv_reg MACINDEX; 195 u_int8_t RSVD8[244]; 196 dv_reg TX0HDP; 197 dv_reg TX1HDP; 198 dv_reg TX2HDP; 199 dv_reg TX3HDP; 200 dv_reg TX4HDP; 201 dv_reg TX5HDP; 202 dv_reg TX6HDP; 203 dv_reg TX7HDP; 204 dv_reg RX0HDP; 205 dv_reg RX1HDP; 206 dv_reg RX2HDP; 207 dv_reg RX3HDP; 208 dv_reg RX4HDP; 209 dv_reg RX5HDP; 210 dv_reg RX6HDP; 211 dv_reg RX7HDP; 212 dv_reg TX0CP; 213 dv_reg TX1CP; 214 dv_reg TX2CP; 215 dv_reg TX3CP; 216 dv_reg TX4CP; 217 dv_reg TX5CP; 218 dv_reg TX6CP; 219 dv_reg TX7CP; 220 dv_reg RX0CP; 221 dv_reg RX1CP; 222 dv_reg RX2CP; 223 dv_reg RX3CP; 224 dv_reg RX4CP; 225 dv_reg RX5CP; 226 dv_reg RX6CP; 227 dv_reg RX7CP; 228} emac_regs; 229 230/* EMAC Wrapper Registers Structure */ 231typedef struct { 232#ifdef DAVINCI_EMAC_VERSION2 233 dv_reg idver; 234 dv_reg softrst; 235 dv_reg emctrl; 236 dv_reg c0rxthreshen; 237 dv_reg c0rxen; 238 dv_reg c0txen; 239 dv_reg c0miscen; 240 dv_reg c1rxthreshen; 241 dv_reg c1rxen; 242 dv_reg c1txen; 243 dv_reg c1miscen; 244 dv_reg c2rxthreshen; 245 dv_reg c2rxen; 246 dv_reg c2txen; 247 dv_reg c2miscen; 248 dv_reg c0rxthreshstat; 249 dv_reg c0rxstat; 250 dv_reg c0txstat; 251 dv_reg c0miscstat; 252 dv_reg c1rxthreshstat; 253 dv_reg c1rxstat; 254 dv_reg c1txstat; 255 dv_reg c1miscstat; 256 dv_reg c2rxthreshstat; 257 dv_reg c2rxstat; 258 dv_reg c2txstat; 259 dv_reg c2miscstat; 260 dv_reg c0rximax; 261 dv_reg c0tximax; 262 dv_reg c1rximax; 263 dv_reg c1tximax; 264 dv_reg c2rximax; 265 dv_reg c2tximax; 266#else 267 u_int8_t RSVD0[4100]; 268 dv_reg EWCTL; 269 dv_reg EWINTTCNT; 270#endif 271} ewrap_regs; 272 273/* EMAC MDIO Registers Structure */ 274typedef struct { 275 dv_reg VERSION; 276 dv_reg CONTROL; 277 dv_reg ALIVE; 278 dv_reg LINK; 279 dv_reg LINKINTRAW; 280 dv_reg LINKINTMASKED; 281 u_int8_t RSVD0[8]; 282 dv_reg USERINTRAW; 283 dv_reg USERINTMASKED; 284 dv_reg USERINTMASKSET; 285 dv_reg USERINTMASKCLEAR; 286 u_int8_t RSVD1[80]; 287 dv_reg USERACCESS0; 288 dv_reg USERPHYSEL0; 289 dv_reg USERACCESS1; 290 dv_reg USERPHYSEL1; 291} mdio_regs; 292 293int davinci_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data); 294int davinci_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data); 295 296typedef struct { 297 char name[64]; 298 int (*init)(int phy_addr); 299 int (*is_phy_connected)(int phy_addr); 300 int (*get_link_speed)(int phy_addr); 301 int (*auto_negotiate)(int phy_addr); 302} phy_t; 303 304#endif /* _DAVINCI_EMAC_H_ */ 305