Searched refs:pdiv (Results 1 - 25 of 39) sorted by relevance

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/linux-master/drivers/clk/tegra/
H A Dclk-tegra124.c153 { .pdiv = 1, .hw_val = 0 },
154 { .pdiv = 2, .hw_val = 1 },
155 { .pdiv = 3, .hw_val = 2 },
156 { .pdiv = 4, .hw_val = 3 },
157 { .pdiv = 5, .hw_val = 4 },
158 { .pdiv = 6, .hw_val = 5 },
159 { .pdiv = 8, .hw_val = 6 },
160 { .pdiv = 10, .hw_val = 7 },
161 { .pdiv = 12, .hw_val = 8 },
162 { .pdiv
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H A Dclk-tegra114.c149 { .pdiv = 1, .hw_val = 0 },
150 { .pdiv = 2, .hw_val = 1 },
151 { .pdiv = 3, .hw_val = 2 },
152 { .pdiv = 4, .hw_val = 3 },
153 { .pdiv = 5, .hw_val = 4 },
154 { .pdiv = 6, .hw_val = 5 },
155 { .pdiv = 8, .hw_val = 6 },
156 { .pdiv = 10, .hw_val = 7 },
157 { .pdiv = 12, .hw_val = 8 },
158 { .pdiv
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H A Dclk-tegra210.c1465 pllx->params->pdiv_tohw[cfg->p].pdiv / 1000);
1486 u32 pdiv; local
1493 p = params->round_p_to_pdiv(p, &pdiv);
1580 { .pdiv = 1, .hw_val = 0 },
1581 { .pdiv = 2, .hw_val = 1 },
1582 { .pdiv = 3, .hw_val = 2 },
1583 { .pdiv = 4, .hw_val = 3 },
1584 { .pdiv = 5, .hw_val = 4 },
1585 { .pdiv = 6, .hw_val = 5 },
1586 { .pdiv
1599 pll_qlin_p_to_pdiv(u32 p, u32 *pdiv) argument
1628 pll_expo_p_to_pdiv(u32 p, u32 *pdiv) argument
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H A Dclk-pll.c486 while (p_tohw->pdiv) {
487 if (p_div <= p_tohw->pdiv)
507 while (p_tohw->pdiv) {
509 return p_tohw->pdiv;
870 int pdiv; local
893 pdiv = 1;
895 pdiv = _hw_to_p_div(hw, cfg.p);
896 if (pdiv < 0) {
897 WARN(1, "Clock %s has invalid pdiv value : 0x%x\n",
899 pdiv
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H A Dclk-tegra20.c267 { .pdiv = 1, .hw_val = 1 },
268 { .pdiv = 0, .hw_val = 0 },
360 { .pdiv = 1, .hw_val = 1 },
361 { .pdiv = 2, .hw_val = 0 },
362 { .pdiv = 0, .hw_val = 0 },
/linux-master/drivers/clk/samsung/
H A Dclk-pll.h56 .pdiv = (_p), \
65 .pdiv = (_p), \
75 .pdiv = (_p), \
85 .pdiv = (_p), \
96 .pdiv = (_p), \
108 unsigned int pdiv; member in struct:samsung_pll_rate_table
H A Dclk-pll.c153 u32 pll_con, mdiv, pdiv, sdiv; local
158 pdiv = (pll_con >> PLL2126_PDIV_SHIFT) & PLL2126_PDIV_MASK;
162 do_div(fvco, (pdiv + 2) << sdiv);
186 u32 pll_con, mdiv, pdiv, sdiv; local
191 pdiv = (pll_con >> PLL3000_PDIV_SHIFT) & PLL3000_PDIV_MASK;
195 do_div(fvco, pdiv << sdiv);
223 u32 mdiv, pdiv, sdiv, pll_con; local
228 pdiv = (pll_con >> PLL35XX_PDIV_SHIFT) & PLL35XX_PDIV_MASK;
232 do_div(fvco, (pdiv << sdiv));
245 return (rate->mdiv != old_mdiv || rate->pdiv !
327 u32 mdiv, pdiv, sdiv, pll_con0, pll_con1; local
437 u32 mdiv, pdiv, sdiv, pll_con3; local
525 u32 mdiv, pdiv, sdiv, pll_con3, pll_con5; local
623 u32 mdiv, pdiv, sdiv, pll_con; local
756 u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1, shift; local
885 u32 mdiv, pdiv, sdiv, pll_con; local
925 u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1; local
1004 u32 mdiv, pdiv, sdiv, pll_con; local
1018 samsung_pll2550xx_mp_change(u32 mdiv, u32 pdiv, u32 pll_con) argument
1105 u32 mdiv, pdiv, sdiv, pll_con0, pll_con1; local
1196 u32 mdiv, pdiv, sdiv, pll_con0, pll_con2; local
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/linux-master/drivers/clk/imx/
H A Dclk-pll14xx.c104 static long pll14xx_calc_rate(struct clk_pll14xx *pll, int mdiv, int pdiv, argument
111 pdiv *= 65536;
113 do_div(fout, pdiv << sdiv);
118 static long pll1443x_calc_kdiv(int mdiv, int pdiv, int sdiv, argument
123 /* calc kdiv = round(rate * pdiv * 65536 * 2^sdiv / prate) - (mdiv * 65536) */
124 kdiv = ((rate * ((pdiv * 65536) << sdiv) + prate / 2) / prate) - (mdiv * 65536);
133 int mdiv, pdiv, sdiv, kdiv; local
156 t->pdiv = tt->pdiv;
164 pdiv
248 u32 mdiv, pdiv, sdiv, kdiv, pll_div_ctl0, pll_div_ctl1; local
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/linux-master/drivers/thermal/tegra/
H A Dtegra124-soctherm.c51 .pdiv = 8,
70 .pdiv = 8,
89 .pdiv = 8,
106 .pdiv = 8,
H A Dtegra132-soctherm.c51 .pdiv = 8,
70 .pdiv = 8,
89 .pdiv = 8,
106 .pdiv = 8,
H A Dtegra210-soctherm.c52 .pdiv = 8,
71 .pdiv = 8,
90 .pdiv = 8,
107 .pdiv = 8,
H A Dsoctherm.h65 * @pdiv: the sensor count post-divider to use during runtime
77 u32 pdiv, pdiv_ate, pdiv_mask; member in struct:tegra_tsensor_group
89 u32 tall, tiddq_en, ten_count, pdiv, pdiv_ate, tsample, tsample_ate; member in struct:tegra_tsensor_configuration
H A Dsoctherm-fuse.c134 mult = sensor_group->pdiv * sensor->config->tsample_ate;
/linux-master/drivers/clk/bcm/
H A Dclk-iproc.h82 * ((ndiv_int + ndiv_frac / 2^20) * (ref frequency / pdiv)
88 unsigned int pdiv; member in struct:iproc_pll_vco_param
164 struct iproc_clk_reg_op pdiv; member in struct:iproc_pll_ctrl
H A Dclk-iproc-armpll.c178 * pdiv = ARM PLL pre-divider
183 * ((ndiv * parent clock rate) / pdiv) / mdiv
192 unsigned int pdiv; local
208 pdiv = (val >> IPROC_CLK_PLLARMA_PDIV_SHIFT) &
210 if (pdiv == 0)
211 pdiv = 16;
220 pll->rate = (pll->rate / pdiv) / mdiv;
224 pr_debug("%s: ndiv_int: %u, pdiv: %u, mdiv: %d\n", __func__,
225 (unsigned int)(ndiv >> 20), pdiv, mdiv);
H A Dclk-iproc-pll.c104 vco_out->pdiv = 1;
282 unsigned int pdiv; local
296 val = readl(pll->control_base + ctrl->pdiv.offset);
297 pdiv = (val >> ctrl->pdiv.shift) & bit_mask(ctrl->pdiv.width);
299 if (pdiv != vco->pdiv)
321 if (vco->pdiv == 0)
324 ref_freq = parent_rate / vco->pdiv;
455 unsigned int pdiv; local
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H A Dclk-sr.c43 .pdiv = REG_VAL(0x14, 0, 4),
103 .pdiv = REG_VAL(0x14, 0, 4),
162 .pdiv = REG_VAL(0x14, 0, 4),
197 .pdiv = REG_VAL(0x14, 0, 4),
251 .pdiv = REG_VAL(0x14, 0, 4),
287 .pdiv = REG_VAL(0x4, 26, 4),
332 .pdiv = REG_VAL(0x4, 26, 4),
371 .pdiv = REG_VAL(0x4, 26, 4),
H A Dclk-nsp.c42 .pdiv = REG_VAL(0x18, 24, 3),
99 .pdiv = REG_VAL(0x4, 28, 3),
H A Dclk-ns2.c37 .pdiv = REG_VAL(0x8, 0, 4),
100 .pdiv = REG_VAL(0x8, 0, 4),
162 .pdiv = REG_VAL(0x8, 0, 4),
224 .pdiv = REG_VAL(0x8, 0, 4),
H A Dclk-cygnus.c56 .pdiv = REG_VAL(0x14, 0, 4),
114 .pdiv = REG_VAL(0x4, 26, 4),
169 /* rate (Hz) ndiv_int ndiv_frac pdiv */
192 .pdiv = REG_VAL(0x14, 0, 4),
271 .pdiv = REG_VAL(0x44, 0, 4),
/linux-master/drivers/clk/
H A Dclk-cdce925.c54 u16 pdiv; /* 1..127 for Y2-Y9; 1..1023 for Y1 */ member in struct:clk_cdce925_output
274 static void cdce925_clk_set_pdiv(struct clk_cdce925_output *data, u16 pdiv) argument
280 0x03, (pdiv >> 8) & 0x03);
281 regmap_write(data->chip->regmap, 0x03, pdiv & 0xFF);
284 regmap_update_bits(data->chip->regmap, 0x16, 0x7F, pdiv);
287 regmap_update_bits(data->chip->regmap, 0x17, 0x7F, pdiv);
290 regmap_update_bits(data->chip->regmap, 0x26, 0x7F, pdiv);
293 regmap_update_bits(data->chip->regmap, 0x27, 0x7F, pdiv);
296 regmap_update_bits(data->chip->regmap, 0x36, 0x7F, pdiv);
299 regmap_update_bits(data->chip->regmap, 0x37, 0x7F, pdiv);
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/linux-master/drivers/gpu/drm/i915/display/
H A Dintel_dpll_mgr.c1552 u32 pdiv; member in struct:skl_wrpll_params
1577 params->pdiv = 0;
1580 params->pdiv = 1;
1583 params->pdiv = 2;
1586 params->pdiv = 4;
1794 DPLL_CFGCR2_PDIV(wrpll_params.pdiv) |
2463 static void icl_wrpll_get_multipliers(int bestdiv, int *pdiv, argument
2469 *pdiv = 2;
2473 *pdiv = 2;
2477 *pdiv
2502 icl_wrpll_params_populate(struct skl_wrpll_params *params, u32 dco_freq, u32 ref_freq, int pdiv, int qdiv, int kdiv) argument
2752 int d, best_div = 0, pdiv = 0, qdiv = 0, kdiv = 0; local
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/linux-master/drivers/clk/st/
H A Dclk-flexgen.c39 struct clk_divider pdiv; member in struct:flexgen
143 struct clk_hw *pdiv_hw = &flexgen->pdiv.hw;
159 struct clk_hw *pdiv_hw = &flexgen->pdiv.hw;
179 * pdiv is mainly targeted for low freq results, while fdiv
244 fgxbar->pdiv.lock = lock;
245 fgxbar->pdiv.reg = reg + 0x58 + idx * 4;
246 fgxbar->pdiv.width = 10;
/linux-master/drivers/cpufreq/
H A Dbrcmstb-avs-cpufreq.c107 * unused:31-24, mdiv_p0:23-16, unused:15-14, pdiv:13-10 , ndiv_int:9-0
341 static void brcm_avs_parse_p1(u32 p1, unsigned int *mdiv_p0, unsigned int *pdiv, argument
345 *pdiv = (p1 >> PDIV_SHIFT) & PDIV_MASK;
685 unsigned int ndiv, pdiv; local
691 brcm_avs_parse_p1(pmap.p1, &mdiv_p0, &pdiv, &ndiv);
695 pmap.p1, pmap.p2, ndiv, pdiv, mdiv_p0, mdiv_p1, mdiv_p2,
/linux-master/arch/arm/mach-ep93xx/
H A Dclock.c278 int pdiv = 0, div = 0; local
292 pdiv = __pdiv - 3;
306 /* Set the new pdiv and div bits for the new clock rate */
307 val |= (pdiv << EP93XX_SYSCON_CLKDIV_PDIV_SHIFT) | div;

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