Searched refs:mtk_phy_set_bits (Results 1 - 10 of 10) sorted by relevance

/linux-master/drivers/phy/mediatek/
H A Dphy-mtk-hdmi-mt2701.c55 mtk_phy_set_bits(base + HDMI_CON7, RG_HTPLL_AUTOK_EN);
57 mtk_phy_set_bits(base + HDMI_CON6, RG_HTPLL_POSDIV_MASK);
58 mtk_phy_set_bits(base + HDMI_CON2, RG_HDMITX_EN_MBIAS);
60 mtk_phy_set_bits(base + HDMI_CON6, RG_HTPLL_EN);
61 mtk_phy_set_bits(base + HDMI_CON2, RG_HDMITX_EN_TX_CKLDO);
62 mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_SLDO_MASK);
64 mtk_phy_set_bits(base + HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN);
65 mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_SER_MASK);
66 mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_PRED_MASK);
67 mtk_phy_set_bits(bas
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H A Dphy-mtk-ufs.c65 mtk_phy_set_bits(mmio + MP_GLB_DIG_8C, PLL_PWR_ON);
73 mtk_phy_set_bits(mmio + MP_LN_RX_44, CDR_PWR_ON);
81 mtk_phy_set_bits(mmio + MP_LN_DIG_RX_AC, RX_SQ_EN);
96 mtk_phy_set_bits(mmio + MP_LN_DIG_RX_9C, FSM_DIFZ_FRC);
99 mtk_phy_set_bits(mmio + MP_LN_DIG_RX_AC, FRC_RX_SQ_EN);
103 mtk_phy_set_bits(mmio + MP_LN_RX_44, FRC_CDR_ISO_EN);
104 mtk_phy_set_bits(mmio + MP_LN_RX_44, CDR_ISO_EN);
107 mtk_phy_set_bits(mmio + MP_LN_RX_44, FRC_CDR_PWR_ON);
111 mtk_phy_set_bits(mmio + MP_GLB_DIG_8C, FRC_PLL_ISO_EN);
112 mtk_phy_set_bits(mmi
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H A Dphy-mtk-mipi-dsi-mt8183.c77 mtk_phy_set_bits(base + MIPITX_PLL_PWR, AD_DSI_PLL_SDM_PWR_ON);
84 mtk_phy_set_bits(base + MIPITX_PLL_CON1, RG_DSI_PLL_EN);
96 mtk_phy_set_bits(base + MIPITX_PLL_PWR, AD_DSI_PLL_SDM_ISO_EN);
154 mtk_phy_set_bits(base + MIPITX_CK_CKMODE_EN, DSI_CK_CKMODE_EN);
163 mtk_phy_set_bits(base + MIPITX_D0_SW_CTL_EN, DSI_SW_CTL_EN);
164 mtk_phy_set_bits(base + MIPITX_D1_SW_CTL_EN, DSI_SW_CTL_EN);
165 mtk_phy_set_bits(base + MIPITX_D2_SW_CTL_EN, DSI_SW_CTL_EN);
166 mtk_phy_set_bits(base + MIPITX_D3_SW_CTL_EN, DSI_SW_CTL_EN);
167 mtk_phy_set_bits(base + MIPITX_CK_SW_CTL_EN, DSI_SW_CTL_EN);
H A Dphy-mtk-hdmi-mt8195.c23 mtk_phy_set_bits(hdmi_phy->regs + HDMI_ANA_CTL, REG_ANA_HDMI20_FIFO_EN);
59 mtk_phy_set_bits(regs + HDMI_1_PLL_CFG_0, RG_HDMITXPLL_BP2);
60 mtk_phy_set_bits(regs + HDMI_1_PLL_CFG_2, RG_HDMITXPLL_BC);
64 mtk_phy_set_bits(regs + HDMI_1_PLL_CFG_2, RG_HDMITXPLL_BP);
70 mtk_phy_set_bits(regs + HDMI_1_PLL_CFG_1, RG_HDMITXPLL_RESERVE_BIT12_11);
71 mtk_phy_set_bits(regs + HDMI_1_PLL_CFG_0, RG_HDMITXPLL_TCL_EN);
100 mtk_phy_set_bits(regs + HDMI_1_CFG_3, RG_HDMITX21_SLDOLPF_EN);
102 mtk_phy_set_bits(regs + HDMI_1_PLL_CFG_2, RG_HDMITXPLL_PWD);
108 mtk_phy_set_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_TX_POSDIV_EN);
202 mtk_phy_set_bits(reg
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H A Dphy-mtk-hdmi-mt8173.c92 mtk_phy_set_bits(base + HDMI_CON1, RG_HDMITX_PLL_AUTOK_EN);
93 mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_PLL_POSDIV);
95 mtk_phy_set_bits(base + HDMI_CON1, RG_HDMITX_PLL_BIAS_EN);
97 mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_PLL_EN);
99 mtk_phy_set_bits(base + HDMI_CON1, RG_HDMITX_PLL_BIAS_LPF_EN);
100 mtk_phy_set_bits(base + HDMI_CON1, RG_HDMITX_PLL_TXDIV_EN);
161 mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_PLL_POSDIV);
184 mtk_phy_set_bits(base + HDMI_CON3, RG_HDMITX_PRD_IMP_EN);
232 mtk_phy_set_bits(hdmi_phy->regs + HDMI_CON3,
H A Dphy-mtk-io.h22 static inline void mtk_phy_set_bits(void __iomem *reg, u32 bits) function
H A Dphy-mtk-mipi-dsi-mt8173.c173 mtk_phy_set_bits(base + MIPITX_DSI_CON,
199 mtk_phy_set_bits(base + MIPITX_DSI_PLL_CON1, RG_DSI_MPPLL_SDM_FRA_EN);
201 mtk_phy_set_bits(base + MIPITX_DSI_PLL_CON0, RG_DSI_MPPLL_PLL_EN);
261 mtk_phy_set_bits(mipi_tx->regs + reg, RG_DSI_LNTx_LDOOUT_EN);
272 mtk_phy_set_bits(mipi_tx->regs + MIPITX_DSI_TOP_CON,
H A Dphy-mtk-tphy.c610 mtk_phy_set_bits(phyd + U3P_U3_PHYD_IMPCAL0, P3D_RG_FORCE_TX_IMPEL);
615 mtk_phy_set_bits(phyd + U3P_U3_PHYD_IMPCAL1, P3D_RG_FORCE_RX_IMPEL);
718 mtk_phy_set_bits(com + U3P_USBPHYACR5, PA5_RG_U2_HSTX_SRCAL_EN);
722 mtk_phy_set_bits(fmreg + U3P_U2FREQ_FMMONR1, P2F_RG_FRCK_EN);
734 mtk_phy_set_bits(fmreg + U3P_U2FREQ_FMCR0, P2F_RG_FREQDET_EN);
779 mtk_phy_set_bits(phyd + U3P_U3_PHYD_TOP1, P3D_RG_FORCE_PHY_MODE);
781 mtk_phy_set_bits(u3_banks->chip + U3P_U3_CHIP_GPIO_CTLD,
783 mtk_phy_set_bits(u3_banks->chip + U3P_U3_CHIP_GPIO_CTLE,
794 mtk_phy_set_bits(u3_banks->spllc + U3P_SPLLC_XTALCTL3,
833 mtk_phy_set_bits(co
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H A Dphy-mtk-xsphy.c122 mtk_phy_set_bits(pbase + XSP_USBPHYACR5, P2A5_RG_HSTX_SRCAL_EN);
126 mtk_phy_set_bits(pbase + XSP_U2FREQ_FMMONR1, P2F_RG_FRCK_EN);
133 mtk_phy_set_bits(pbase + XSP_U2FREQ_FMCR0, P2F_RG_FREQDET_EN);
175 mtk_phy_set_bits(pbase + XSP_USBPHYACR0, P2A0_RG_INTR_EN);
184 mtk_phy_set_bits(pbase + XSP_USBPHYACR6, P2A6_RG_OTG_VBUSCMP_EN);
H A Dphy-mtk-mipi-csi-0-5.c136 mtk_phy_set_bits(base + MIPI_RX_ANA40_CSIXA, 0x90);

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