1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2021 MediaTek Inc.
4 *
5 * Author: Chunfeng Yun <chunfeng.yun@mediatek.com>
6 */
7
8#ifndef __PHY_MTK_H__
9#define __PHY_MTK_H__
10
11#include <linux/bitfield.h>
12#include <linux/io.h>
13
14static inline void mtk_phy_clear_bits(void __iomem *reg, u32 bits)
15{
16	u32 tmp = readl(reg);
17
18	tmp &= ~bits;
19	writel(tmp, reg);
20}
21
22static inline void mtk_phy_set_bits(void __iomem *reg, u32 bits)
23{
24	u32 tmp = readl(reg);
25
26	tmp |= bits;
27	writel(tmp, reg);
28}
29
30static inline void mtk_phy_update_bits(void __iomem *reg, u32 mask, u32 val)
31{
32	u32 tmp = readl(reg);
33
34	tmp &= ~mask;
35	tmp |= val & mask;
36	writel(tmp, reg);
37}
38
39/* field @mask shall be constant and continuous */
40#define mtk_phy_update_field(reg, mask, val) \
41({ \
42	BUILD_BUG_ON_MSG(!__builtin_constant_p(mask), "mask is not constant"); \
43	mtk_phy_update_bits(reg, mask, FIELD_PREP(mask, val)); \
44})
45
46#endif
47