phy/mediatek/phy-mtk-ufs.c

65 	mtk_phy_set_bits(mmio + MP_GLB_DIG_8C, PLL_PWR_ON);
73 	mtk_phy_set_bits(mmio + MP_LN_RX_44, CDR_PWR_ON);
81 	mtk_phy_set_bits(mmio + MP_LN_DIG_RX_AC, RX_SQ_EN);
96 	mtk_phy_set_bits(mmio + MP_LN_DIG_RX_9C, FSM_DIFZ_FRC);
99 	mtk_phy_set_bits(mmio + MP_LN_DIG_RX_AC, FRC_RX_SQ_EN);
103 	mtk_phy_set_bits(mmio + MP_LN_RX_44, FRC_CDR_ISO_EN);
104 	mtk_phy_set_bits(mmio + MP_LN_RX_44, CDR_ISO_EN);
107 	mtk_phy_set_bits(mmio + MP_LN_RX_44, FRC_CDR_PWR_ON);
111 	mtk_phy_set_bits(mmio + MP_GLB_DIG_8C, FRC_PLL_ISO_EN);
112 	mtk_phy_set_bits(mmio + MP_GLB_DIG_8C, PLL_ISO_EN);
115 	mtk_phy_set_bits(mmio + MP_GLB_DIG_8C, FRC_FRC_PWR_ON);