Searched refs:mtk_phy_clear_bits (Results 1 - 9 of 9) sorted by relevance

/linux-master/drivers/phy/mediatek/
H A Dphy-mtk-hdmi-mt2701.c56 mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_RLH_EN);
77 mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_DRV_MASK);
78 mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_PRED_MASK);
79 mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_SER_MASK);
80 mtk_phy_clear_bits(base + HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN);
82 mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_SLDO_MASK);
83 mtk_phy_clear_bits(base + HDMI_CON2, RG_HDMITX_EN_TX_CKLDO);
84 mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_EN);
86 mtk_phy_clear_bits(base + HDMI_CON2, RG_HDMITX_EN_MBIAS);
87 mtk_phy_clear_bits(bas
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H A Dphy-mtk-ufs.c66 mtk_phy_clear_bits(mmio + MP_GLB_DIG_8C, FRC_FRC_PWR_ON);
69 mtk_phy_clear_bits(mmio + MP_GLB_DIG_8C, PLL_ISO_EN);
70 mtk_phy_clear_bits(mmio + MP_GLB_DIG_8C, FRC_PLL_ISO_EN);
74 mtk_phy_clear_bits(mmio + MP_LN_RX_44, FRC_CDR_PWR_ON);
77 mtk_phy_clear_bits(mmio + MP_LN_RX_44, CDR_ISO_EN);
78 mtk_phy_clear_bits(mmio + MP_LN_RX_44, FRC_CDR_ISO_EN);
82 mtk_phy_clear_bits(mmio + MP_LN_DIG_RX_AC, FRC_RX_SQ_EN);
88 mtk_phy_clear_bits(mmio + MP_LN_DIG_RX_9C, FSM_DIFZ_FRC);
100 mtk_phy_clear_bits(mmio + MP_LN_DIG_RX_AC, RX_SQ_EN);
108 mtk_phy_clear_bits(mmi
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H A Dphy-mtk-mipi-dsi-mt8183.c75 mtk_phy_clear_bits(base + MIPITX_PLL_CON4, RG_DSI_PLL_IBIAS);
78 mtk_phy_clear_bits(base + MIPITX_PLL_CON1, RG_DSI_PLL_EN);
80 mtk_phy_clear_bits(base + MIPITX_PLL_PWR, AD_DSI_PLL_SDM_ISO_EN);
94 mtk_phy_clear_bits(base + MIPITX_PLL_CON1, RG_DSI_PLL_EN);
97 mtk_phy_clear_bits(base + MIPITX_PLL_PWR, AD_DSI_PLL_SDM_PWR_ON);
143 mtk_phy_clear_bits(base + MIPITX_D0_SW_CTL_EN, DSI_SW_CTL_EN);
144 mtk_phy_clear_bits(base + MIPITX_D1_SW_CTL_EN, DSI_SW_CTL_EN);
145 mtk_phy_clear_bits(base + MIPITX_D2_SW_CTL_EN, DSI_SW_CTL_EN);
146 mtk_phy_clear_bits(base + MIPITX_D3_SW_CTL_EN, DSI_SW_CTL_EN);
147 mtk_phy_clear_bits(bas
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H A Dphy-mtk-hdmi-mt8195.c39 mtk_phy_clear_bits(regs + HDMI20_CLK_CFG, REG_TXC_DIV);
47 mtk_phy_clear_bits(regs + HDMI_CTL_3, REG_HDMITX_REF_XTAL_SEL);
48 mtk_phy_clear_bits(regs + HDMI_CTL_3, REG_HDMITX_REF_RESPLL_SEL);
51 mtk_phy_clear_bits(regs + HDMI_1_CFG_10, RG_HDMITXPLL_REF_CK_SEL);
65 mtk_phy_clear_bits(regs + HDMI_1_PLL_CFG_0, RG_HDMITXPLL_IBAND_FIX_EN);
66 mtk_phy_clear_bits(regs + HDMI_1_PLL_CFG_1, RG_HDMITXPLL_RESERVE_BIT14);
67 mtk_phy_clear_bits(regs + HDMI_1_PLL_CFG_2, RG_HDMITXPLL_HIKVCO);
97 mtk_phy_clear_bits(regs + HDMI_1_CFG_10, RG_HDMITX21_VREF_SEL);
99 mtk_phy_clear_bits(regs + HDMI_1_CFG_10, RG_HDMITX21_BIAS_PE_VREF_SELB);
109 mtk_phy_clear_bits(reg
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H A Dphy-mtk-mipi-dsi-mt8173.c180 mtk_phy_clear_bits(base + MIPITX_DSI_PLL_CON0, RG_DSI_MPPLL_PLL_EN);
205 mtk_phy_clear_bits(base + MIPITX_DSI_PLL_CON1, RG_DSI_MPPLL_SDM_SSC_EN);
221 mtk_phy_clear_bits(base + MIPITX_DSI_PLL_CON0, RG_DSI_MPPLL_PLL_EN);
223 mtk_phy_clear_bits(base + MIPITX_DSI_PLL_TOP, RG_DSI_MPPLL_PRESERVE);
229 mtk_phy_clear_bits(base + MIPITX_DSI_TOP_CON, RG_DSI_LNT_HS_BIAS_EN);
231 mtk_phy_clear_bits(base + MIPITX_DSI_CON,
234 mtk_phy_clear_bits(base + MIPITX_DSI_BG_CON,
237 mtk_phy_clear_bits(base + MIPITX_DSI_PLL_CON0, RG_DSI_MPPLL_DIV_MSK);
263 mtk_phy_clear_bits(mipi_tx->regs + MIPITX_DSI_TOP_CON,
277 mtk_phy_clear_bits(mipi_t
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H A Dphy-mtk-hdmi-mt8173.c94 mtk_phy_clear_bits(base + HDMI_CON3, RG_HDMITX_MHLCK_EN);
110 mtk_phy_clear_bits(base + HDMI_CON1, RG_HDMITX_PLL_TXDIV_EN);
111 mtk_phy_clear_bits(base + HDMI_CON1, RG_HDMITX_PLL_BIAS_LPF_EN);
113 mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_PLL_EN);
115 mtk_phy_clear_bits(base + HDMI_CON1, RG_HDMITX_PLL_BIAS_EN);
116 mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_PLL_POSDIV);
117 mtk_phy_clear_bits(base + HDMI_CON1, RG_HDMITX_PLL_AUTOK_EN);
179 mtk_phy_clear_bits(base + HDMI_CON3, RG_HDMITX_PRD_IMP_EN);
240 mtk_phy_clear_bits(hdmi_phy->regs + HDMI_CON3,
H A Dphy-mtk-io.h14 static inline void mtk_phy_clear_bits(void __iomem *reg, u32 bits) function
H A Dphy-mtk-tphy.c743 mtk_phy_clear_bits(fmreg + U3P_U2FREQ_FMCR0, P2F_RG_FREQDET_EN);
746 mtk_phy_clear_bits(fmreg + U3P_U2FREQ_FMMONR1, P2F_RG_FRCK_EN);
766 mtk_phy_clear_bits(com + U3P_USBPHYACR5, PA5_RG_U2_HSTX_SRCAL_EN);
787 mtk_phy_clear_bits(u3_banks->chip + U3P_U3_CHIP_GPIO_CTLD,
789 mtk_phy_clear_bits(u3_banks->chip + U3P_U3_CHIP_GPIO_CTLE,
845 mtk_phy_clear_bits(com + U3P_U2PHYDTM0, P2C_FORCE_UART_EN | P2C_FORCE_SUSPENDM);
847 mtk_phy_clear_bits(com + U3P_U2PHYDTM0,
850 mtk_phy_clear_bits(com + U3P_U2PHYDTM1, P2C_RG_UART_EN);
855 mtk_phy_clear_bits(com + U3P_USBPHYACR5, PA5_RG_U2_HS_100U_U3_EN);
857 mtk_phy_clear_bits(co
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H A Dphy-mtk-xsphy.c142 mtk_phy_clear_bits(pbase + XSP_U2FREQ_FMCR0, P2F_RG_FREQDET_EN);
145 mtk_phy_clear_bits(pbase + XSP_U2FREQ_FMMONR1, P2F_RG_FRCK_EN);
164 mtk_phy_clear_bits(pbase + XSP_USBPHYACR5, P2A5_RG_HSTX_SRCAL_EN);
173 mtk_phy_clear_bits(pbase + XSP_USBPHYACR6, P2A6_RG_BC11_SW_EN);
199 mtk_phy_clear_bits(pbase + XSP_USBPHYACR6, P2A6_RG_OTG_VBUSCMP_EN);

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