phy/mediatek/phy-mtk-hdmi-mt2701.c

56 	mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_RLH_EN);
77 	mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_DRV_MASK);
78 	mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_PRED_MASK);
79 	mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_SER_MASK);
80 	mtk_phy_clear_bits(base + HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN);
82 	mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_SLDO_MASK);
83 	mtk_phy_clear_bits(base + HDMI_CON2, RG_HDMITX_EN_TX_CKLDO);
84 	mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_EN);
86 	mtk_phy_clear_bits(base + HDMI_CON2, RG_HDMITX_EN_MBIAS);
87 	mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_POSDIV_MASK);
88 	mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_RLH_EN);
89 	mtk_phy_clear_bits(base + HDMI_CON7, RG_HTPLL_AUTOK_EN);
126 	mtk_phy_clear_bits(base + HDMI_CON1, RG_HDMITX_PRED_IMP);
128 	mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_IMP_MASK);
182 	mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_RLH_EN);
201 	mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_DRV_MASK);
202 	mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_PRED_MASK);
203 	mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_SER_MASK);
204 	mtk_phy_clear_bits(base + HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN);
206 	mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_SLDO_MASK);
207 	mtk_phy_clear_bits(base + HDMI_CON2, RG_HDMITX_EN_TX_CKLDO);
208 	mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_EN);
210 	mtk_phy_clear_bits(base + HDMI_CON2, RG_HDMITX_EN_MBIAS);
211 	mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_POSDIV_MASK);
212 	mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_RLH_EN);
213 	mtk_phy_clear_bits(base + HDMI_CON7, RG_HTPLL_AUTOK_EN);