Searched refs:miss (Results 1 - 25 of 33) sorted by relevance

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/linux-master/tools/testing/selftests/mm/
H A Dvm_util.h50 bool miss, bool wp, bool minor);
53 bool miss, bool wp, bool minor, uint64_t *ioctls);
H A Dvm_util.c304 bool miss, bool wp, bool minor, uint64_t *ioctls)
310 if (miss)
330 bool miss, bool wp, bool minor)
333 miss, wp, minor, NULL);
303 uffd_register_with_ioctls(int uffd, void *addr, uint64_t len, bool miss, bool wp, bool minor, uint64_t *ioctls) argument
329 uffd_register(int uffd, void *addr, uint64_t len, bool miss, bool wp, bool minor) argument
H A Duffd-unit-tests.c1267 do_register_ioctls_test(uffd_test_args_t *args, bool miss, bool wp, bool minor) argument
1274 miss, wp, minor, &ioctls);
1284 (!miss && !wp && !minor)) {
1286 err("register (miss=%d, wp=%d, minor=%d) failed "
1287 "with wrong errno=%d", miss, wp, minor, ret);
1292 if (miss)
1301 "(miss=%d, wp=%d, minor=%d): expected=0x%"PRIx64", "
1302 "returned=0x%"PRIx64, miss, wp, minor, expected, ioctls);
1310 int miss, wp, minor; local
1312 for (miss
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/linux-master/drivers/net/ethernet/arc/
H A Demac_main.c276 unsigned int miss; local
278 miss = arc_reg_get(priv, R_MISS);
279 if (miss) {
280 stats->rx_errors += miss;
281 stats->rx_missed_errors += miss;
282 priv->rx_missed_errors += miss;
645 unsigned long miss, rxerr; local
649 miss = arc_reg_get(priv, R_MISS);
655 stats->rx_errors += miss;
661 stats->rx_missed_errors += miss;
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/linux-master/net/wireless/
H A Dwext-proc.c64 stats->discard.misc, stats->miss.beacon);
/linux-master/drivers/dma-buf/
H A Dst-dma-fence.c462 unsigned long miss = 0; local
492 miss++;
506 t->id, pass, miss,
523 __func__, t->id, pass, miss);
/linux-master/drivers/md/bcache/
H A Drequest.c275 * From a cache miss, we can just insert the keys for the data
510 * Read from a single key, handling the initial cache miss if the key starts in
535 /* if this was a complete miss we shouldn't get here */
825 * We had a cache miss; cache_bio now contains data ready to be inserted
883 struct bio *miss, *cache_bio; local
889 miss = bio_next_split(bio, sectors, GFP_NOIO, &s->d->bio_split);
890 ret = miss == bio ? MAP_DONE : MAP_CONTINUE;
909 miss = bio_next_split(bio, s->insert_bio_sectors, GFP_NOIO,
913 ret = miss == bio ? MAP_DONE : -EINTR;
915 cache_bio = bio_alloc_bioset(miss
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/linux-master/arch/mips/kernel/
H A Dentry.S47 local_irq_disable # make sure we dont miss an
/linux-master/tools/perf/util/
H A Dbpf-filter.l126 miss { return constant(PERF_MEM_SNOOP_MISS); }
H A Dmem-events.c288 u64 hit, miss; local
297 miss = m & PERF_MEM_TLB_MISS;
315 if (miss)
316 l += scnprintf(out + l, sz - l, " miss");
406 memcpy(hit_miss, "miss", 4);
H A Dparse-events.l172 lc_op_result (load|loads|read|store|stores|write|prefetch|prefetches|speculative-read|speculative-load|refs|Reference|ops|access|misses|miss)
292 * state we need to put the escaping char back, so we dont miss it.
/linux-master/arch/arc/kernel/
H A Dentry-arcv2.S34 VECTOR EV_TLBMissI ; Instruction TLB miss
35 VECTOR EV_TLBMissD ; Data TLB miss
H A Dentry-compact.S105 VECTOR EV_TLBMissI ; 0x108, Instruction TLB miss (0x21)
106 VECTOR EV_TLBMissD ; 0x110, Data TLB miss (0x22)
/linux-master/lib/
H A Dbtree.c329 goto miss;
333 goto miss;
338 goto miss;
346 goto miss;
349 miss:
/linux-master/scripts/
H A Dspdxcheck.py38 def update(self, fname, basedir, miss):
40 self.missing += miss
41 if miss:
/linux-master/drivers/perf/
H A Dqcom_l3_pmu.c604 * perf stat -a -e l3cache_0_0/event=read-miss/ ls
655 L3CACHE_EVENT_ATTR(read-miss, L3_EVENT_READ_MISS),
657 L3CACHE_EVENT_ATTR(read-miss-d-side, L3_EVENT_READ_MISS_D),
659 L3CACHE_EVENT_ATTR(write-miss, L3_EVENT_WRITE_MISS),
/linux-master/include/linux/
H A Dcompiler_types.h178 unsigned long miss; member in struct:ftrace_branch_data::__anon391::__anon393
/linux-master/drivers/net/ethernet/mellanox/mlx5/core/lib/
H A Dmacsec_fs.c150 struct mlx5_macsec_miss miss; member in struct:mlx5_macsec_rx_roce
343 /* reserve entry for the match all miss group and rule */
461 /* Tx crypto table Default miss rule */
467 mlx5_core_err(mdev, "Failed to add MACsec Tx table default miss rule %d\n", err);
482 /* Tx check table Default miss group/rule */
982 static void macsec_fs_rx_roce_miss_destroy(struct mlx5_macsec_miss *miss) argument
984 mlx5_del_flow_rules(miss->rule);
985 mlx5_destroy_flow_group(miss->g);
1000 macsec_fs_rx_roce_miss_destroy(&roce->miss);
1230 /* IP check ft has no miss rul
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/linux-master/drivers/net/ethernet/mellanox/mlx5/core/en_accel/
H A Dipsec_fs.c454 struct mlx5e_ipsec_miss *miss,
473 miss->group = mlx5_create_flow_group(ft, flow_group_in);
474 if (IS_ERR(miss->group)) {
475 err = PTR_ERR(miss->group);
481 /* Create miss rule */
482 miss->rule = mlx5_add_flow_rules(ft, spec, &flow_act, dest, 1);
483 if (IS_ERR(miss->rule)) {
484 mlx5_destroy_flow_group(miss->group);
485 err = PTR_ERR(miss->rule);
452 ipsec_miss_create(struct mlx5_core_dev *mdev, struct mlx5_flow_table *ft, struct mlx5e_ipsec_miss *miss, struct mlx5_flow_destination *dest) argument
/linux-master/drivers/block/
H A Dps3vram.c66 unsigned int miss; member in struct:ps3vram_cache
394 cache->miss++;
515 seq_printf(m, "hit:%u\nmiss:%u\n", priv->cache.hit, priv->cache.miss);
/linux-master/include/uapi/linux/
H A Dwireless.h888 struct iw_missed miss; /* Packet missed counts */ member in struct:iw_statistics
/linux-master/net/bridge/
H A Dbr_private.h769 static inline void br_tc_skb_miss_set(struct sk_buff *skb, bool miss) argument
778 ext->l2_miss = miss;
781 if (!miss)
789 static inline void br_tc_skb_miss_set(struct sk_buff *skb, bool miss) argument
/linux-master/kernel/sched/
H A Dtopology.c1360 int count = 0, miss = 0; local
1372 ++miss;
1381 if (miss)
/linux-master/arch/sparc/lib/
H A DM7memcpy.S435 ! line (similar to prefetching) to avoid overfilling STQ or miss buffers.
452 ! the store miss buffer. Then the matching stores for all those
/linux-master/tools/testing/selftests/net/openvswitch/
H A Dovs-dpctl.py1435 OVS_PACKET_CMD_MISS = 1 # Flow table miss
1468 up.miss(msg)
2008 def miss(self, packetmsg): member in class:OvsFlow

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