Searched refs:microcode (Results 1 - 25 of 36) sorted by relevance

12

/linux-master/arch/x86/kernel/cpu/microcode/
H A DMakefile2 microcode-y := core.o
3 obj-$(CONFIG_MICROCODE) += microcode.o
4 microcode-$(CONFIG_CPU_SUP_INTEL) += intel.o
5 microcode-$(CONFIG_CPU_SUP_AMD) += amd.o
H A Dintel.c8 * Intel CPU microcode early update for Linux
13 #define pr_fmt(fmt) "microcode: " fmt
32 static const char ucode_path[] = "kernel/x86/microcode/GenuineIntel.bin";
36 /* Current microcode patch used in early patching on the APs. */
43 /* microcode format is extended from prescott processors */
124 * intel_microcode_sanity_check() - Sanity check microcode file.
125 * @mc: Pointer to the microcode file contents.
127 * @hdr_type: Type of file, i.e. normal microcode file or In Field Scan file.
128 * Validate if the microcode header type matches with the type
150 pr_err("Error: bad microcode dat
[all...]
H A Dinternal.h9 #include <asm/microcode.h>
63 * In early loading microcode phase on BSP, boot_cpu_data is not set up yet.
H A Dcore.c9 * X86 CPU microcode early update for Linux:
15 * This driver allows to upgrade microcode on x86 processors.
18 #define pr_fmt(fmt) "microcode: " fmt
253 * is loading microcode in order to avoid any negative interactions caused by
256 * - In addition, microcode update on the cores must be serialized until this
506 * while the primary thread updates the microcode. Instrumentation can end
511 * microcode update handles this correctly. It's only the sibling code
541 int old_rev = boot_cpu_data.microcode;
545 pr_err("Late microcode loading without minimal revision check.\n");
554 * Take a snapshot before the microcode updat
[all...]
H A Damd.c5 * This driver allows to upgrade microcode on F10h AMD
22 #define pr_fmt(fmt) "microcode: " fmt
32 #include <asm/microcode.h>
95 * This points to the current valid container of microcode patches which we will
97 * microcode patch we found to match.
109 * format. See Documentation/arch/x86/microcode.rst
112 ucode_path[] __maybe_unused = "kernel/x86/microcode/AuthenticAMD.bin";
131 * Check whether there is a valid microcode container file at the beginning
139 pr_debug("Truncated microcode container header.\n");
166 pr_debug("Wrong microcode containe
[all...]
/linux-master/drivers/crypto/cavium/cpt/
H A Dcptpf.h22 struct microcode { struct
53 struct microcode mcode[CPT_MAX_CORE_GROUPS];
54 u8 next_mc_idx; /* next microcode index */
H A Dcptpf_main.c122 static int cpt_load_microcode(struct cpt_device *cpt, struct microcode *mcode)
134 dev_err(dev, "microcode size is 0\n");
149 /* Point to microcode for each core of the group */
160 static int do_cpt_init(struct cpt_device *cpt, struct microcode *mcode)
178 dev_err(dev, "Can't load, all eight microcode groups in use");
187 /* Load microcode for AE engines */
207 dev_err(dev, "Can't load, all eight microcode groups in use");
216 /* Load microcode for SE engines */
257 struct microcode *mcode;
282 dev_err(dev, "Unable to allocate space for microcode");
[all...]
H A Dcptpf_mbox.c61 struct microcode *mcode = cpt->mcode;
/linux-master/arch/x86/include/uapi/asm/
H A Dmce.h37 __u32 microcode; /* Microcode revision */ member in struct:mce
/linux-master/arch/x86/kernel/cpu/
H A Dmatch.c86 if (!res || res->x86_microcode_rev > boot_cpu_data.microcode)
H A DMakefile51 obj-$(CONFIG_MICROCODE) += microcode/
H A Dproc.c85 if (c->microcode)
86 seq_printf(m, "microcode\t: 0x%x\n", c->microcode);
H A Dhygon.c127 rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy);
H A Dintel.c23 #include <asm/microcode.h>
129 * Early microcode releases for the Spectre v2 mitigation were broken.
131 * - https://newsroom.intel.com/wp-content/uploads/sites/11/2018/03/microcode-update-guidance.pdf
134 * - Release note from 20180108 microcode release
139 u32 microcode; member in struct:sku_microcode
170 * We know that the hypervisor lie to us on the microcode version so
182 return (c->microcode <= spectre_bad_microcodes[i].microcode);
289 c->microcode = intel_get_microcode_revision();
296 pr_warn("Intel Spectre v2 broken microcode detecte
[all...]
H A Damd.c542 rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy);
619 /* On C+ stepping K8 rep microcode works well for copy/memset */
802 * updated microcode at the time of writing (March 2023).
869 if (boot_cpu_data.microcode < good_rev)
884 pr_notice_once("Zenbleed: please update your microcode for the most optimal fix\n");
/linux-master/arch/x86/kernel/
H A Dhead32.c22 #include <asm/microcode.h>
H A Dhead64.c38 #include <asm/microcode.h>
481 * Load microcode early on BSP.
H A Dnmi.c36 #include <asm/microcode.h>
/linux-master/drivers/soc/fsl/qe/
H A Dqe.c400 * Upload a QE microcode
403 * the actual uploading of the microcode.
413 "uploading microcode '%s' version %u.%u.%u\n",
417 "uploading microcode '%s'\n", ucode->id);
431 * Upload a microcode to the I-RAM at a specific address.
433 * See Documentation/arch/powerpc/qe_firmware.rst for information on QE microcode
443 * all of the microcode structures, minus the CRC.
467 printk(KERN_ERR "qe-firmware: not a microcode\n");
484 calc_size = struct_size(firmware, microcode, firmware->count);
488 * For situations where the second RISC uses the same microcode
[all...]
/linux-master/drivers/scsi/
H A Dwd33c93.h217 uchar microcode; /* microcode rev */ member in struct:WD33C93_hostdata
/linux-master/arch/x86/kernel/cpu/mce/
H A Dinject.c122 m->microcode = boot_cpu_data.microcode;
/linux-master/include/xen/interface/
H A Dplatform.h88 GUEST_HANDLE(void) data; /* Pointer to microcode data */
89 uint32_t length; /* Length of microcode data. */
497 struct xenpf_microcode_update microcode; member in union:xen_platform_op::__anon867
/linux-master/arch/x86/power/
H A Dcpu.c29 #include <asm/microcode.h>
275 * This needs to happen after the microcode has been updated upon resume
276 * because some of the MSRs are "emulated" in microcode.
/linux-master/drivers/platform/x86/intel/ifs/
H A Dload.c7 #include <asm/microcode.h>
/linux-master/arch/x86/include/asm/
H A Dprocessor.h158 u32 microcode; member in struct:cpuinfo_x86

Completed in 274 milliseconds

12