Searched refs:membase (Results 1 - 25 of 208) sorted by relevance

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/linux-master/drivers/media/pci/mgb4/
H A Dmgb4_regs.c17 regs->membase = ioremap(regs->mapbase, regs->mapsize);
18 if (!regs->membase) {
28 iounmap(regs->membase);
H A Dmgb4_regs.h15 void __iomem *membase; member in struct:mgb4_regs
19 iowrite32(val, (regs)->membase + (offset))
21 ioread32((regs)->membase + (offset))
/linux-master/arch/mips/ralink/
H A Dbootrom.c13 static void __iomem *membase = (void __iomem *) KSEG1ADDR(BOOTROM_OFFSET); variable
17 seq_write(s, membase, BOOTROM_SIZE);
/linux-master/drivers/net/mdio/
H A Dmdio-ipq4019.c52 void __iomem *membase; member in struct:ipq4019_mdio_data
63 return readl_poll_timeout(priv->membase + MDIO_CMD_REG, busy,
78 data = readl(priv->membase + MDIO_MODE_REG);
82 writel(data, priv->membase + MDIO_MODE_REG);
85 writel((mii_id << 8) | mmd, priv->membase + MDIO_ADDR_REG);
88 writel(reg, priv->membase + MDIO_DATA_WRITE_REG);
93 writel(cmd, priv->membase + MDIO_CMD_REG);
101 writel(cmd, priv->membase + MDIO_CMD_REG);
107 return readl(priv->membase + MDIO_DATA_READ_REG);
119 data = readl(priv->membase
[all...]
H A Dmdio-sun4i.c32 void __iomem *membase; member in struct:sun4i_mdio_data
43 writel((mii_id << 8) | regnum, data->membase + EMAC_MAC_MADR_REG);
45 writel(0x1, data->membase + EMAC_MAC_MCMD_REG);
49 while (readl(data->membase + EMAC_MAC_MIND_REG) & 0x1) {
56 writel(0x0, data->membase + EMAC_MAC_MCMD_REG);
58 value = readl(data->membase + EMAC_MAC_MRDD_REG);
70 writel((mii_id << 8) | regnum, data->membase + EMAC_MAC_MADR_REG);
72 writel(0x1, data->membase + EMAC_MAC_MCMD_REG);
76 while (readl(data->membase + EMAC_MAC_MIND_REG) & 0x1) {
83 writel(0x0, data->membase
[all...]
/linux-master/drivers/tty/serial/
H A Dmilbeaut_usio.c67 writew(readw(port->membase + MLB_USIO_REG_FCR) & ~MLB_USIO_FCR_FTIE,
68 port->membase + MLB_USIO_REG_FCR);
69 writeb(readb(port->membase + MLB_USIO_REG_SCR) & ~MLB_USIO_SCR_TBIE,
70 port->membase + MLB_USIO_REG_SCR);
78 writew(readw(port->membase + MLB_USIO_REG_FCR) & ~MLB_USIO_FCR_FTIE,
79 port->membase + MLB_USIO_REG_FCR);
80 writeb(readb(port->membase + MLB_USIO_REG_SCR) &
82 port->membase + MLB_USIO_REG_SCR);
85 writew(port->x_char, port->membase + MLB_USIO_REG_DR);
96 (readw(port->membase
[all...]
H A Dtimbuart.c42 u32 ier = ioread32(port->membase + TIMBUART_IER) & ~RXFLAGS;
43 iowrite32(ier, port->membase + TIMBUART_IER);
49 u32 ier = ioread32(port->membase + TIMBUART_IER) & ~TXBAE;
50 iowrite32(ier, port->membase + TIMBUART_IER);
64 u32 isr = ioread32(port->membase + TIMBUART_ISR);
72 u8 ctl = ioread8(port->membase + TIMBUART_CTRL) |
75 iowrite8(ctl, port->membase + TIMBUART_CTRL);
76 iowrite32(TXBF, port->membase + TIMBUART_ISR);
84 while (ioread32(port->membase + TIMBUART_ISR) & RXDP) {
85 u8 ch = ioread8(port->membase
[all...]
H A Dimx_earlycon.c21 while (readl_relaxed(port->membase + IMX21_UTS) & UTS_TXFULL)
24 writel_relaxed(ch, port->membase + URTX0);
38 if (!dev->port.membase)
H A Dmcf.c62 return (readb(port->membase + MCFUART_USR) & MCFUART_USR_TXEMPTY) ?
73 sigs = (readb(port->membase + MCFUART_UIPR) & MCFUART_UIPR_CTS) ?
91 writeb(MCFUART_UOP_RTS, port->membase + MCFUART_UOP1);
93 writeb(MCFUART_UOP_RTS, port->membase + MCFUART_UOP0);
104 writeb(MCFUART_UCR_TXENABLE, port->membase + MCFUART_UCR);
106 writeb(MCFUART_UOP_RTS, port->membase + MCFUART_UOP1);
109 writeb(pp->imr, port->membase + MCFUART_UIMR);
119 writeb(pp->imr, port->membase + MCFUART_UIMR);
129 writeb(pp->imr, port->membase + MCFUART_UIMR);
140 writeb(MCFUART_UCR_CMDBREAKSTART, port->membase
[all...]
H A Damba-pl010.c65 cr = readb(uap->port.membase + UART010_CR);
67 writel(cr, uap->port.membase + UART010_CR);
76 cr = readb(uap->port.membase + UART010_CR);
78 writel(cr, uap->port.membase + UART010_CR);
87 cr = readb(uap->port.membase + UART010_CR);
89 writel(cr, uap->port.membase + UART010_CR);
97 cr = readb(uap->port.membase + UART010_CR);
99 writel(cr, uap->port.membase + UART010_CR);
108 cr = readb(uap->port.membase + UART010_CR);
110 writel(cr, uap->port.membase
[all...]
H A Dlpc32xx_hs.c103 port->membase))) == 0)
117 port->membase))) < 32)
128 writel((u32)ch, LPC32XX_HSUART_FIFO(port->membase));
164 if (!port->membase)
240 while ((readl(LPC32XX_HSUART_LEVEL(port->membase)) > 0) &&
242 readl(LPC32XX_HSUART_FIFO(port->membase));
251 tmp = readl(LPC32XX_HSUART_FIFO(port->membase));
259 LPC32XX_HSUART_IIR(port->membase));
268 tmp = readl(LPC32XX_HSUART_FIFO(port->membase));
276 u32 level = readl(LPC32XX_HSUART_LEVEL(port->membase));
[all...]
H A Dxilinx_uartps.c248 while ((readl(port->membase + CDNS_UART_SR) &
251 rxbs_status = readl(port->membase + CDNS_UART_RXBS);
252 data = readl(port->membase + CDNS_UART_FIFO);
336 val = readl(cdns_uart->port->membase + CDNS_UART_MODEMCR);
341 writel(val, cdns_uart->port->membase + CDNS_UART_MODEMCR);
383 status = readl(port->membase + CDNS_UART_SR);
433 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IDR);
439 !(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXFULL)) {
441 writel(xmit->buf[xmit->tail], port->membase + CDNS_UART_FIFO);
450 writel(CDNS_UART_IXR_TXEMPTY, cdns_uart->port->membase
[all...]
H A Dqcom_geni_serial.c193 uport->membase = devm_platform_ioremap_resource(pdev, 0);
194 if (IS_ERR(uport->membase))
195 return PTR_ERR(uport->membase);
196 port->se.base = uport->membase;
216 geni_ios = readl(uport->membase + SE_GENI_IOS);
238 writel(uart_manual_rfr, uport->membase + SE_UART_MANUAL_RFR);
260 return readl(uport->membase + SE_GENI_STATUS) & M_GENI_CMD_ACTIVE;
265 return readl(uport->membase + SE_GENI_STATUS) & S_GENI_CMD_ACTIVE;
297 reg = readl(uport->membase + offset);
310 writel(xmit_size, uport->membase
[all...]
/linux-master/drivers/net/ethernet/allwinner/
H A Dsun4i-emac.c77 void __iomem *membase; member in struct:emac_board_info
108 reg_val = readl(db->membase + EMAC_MAC_SUPP_REG);
112 writel(reg_val, db->membase + EMAC_MAC_SUPP_REG);
121 reg_val = readl(db->membase + EMAC_MAC_CTL1_REG);
125 writel(reg_val, db->membase + EMAC_MAC_CTL1_REG);
203 writel(0, db->membase + EMAC_CTL_REG);
205 writel(EMAC_CTL_RESET, db->membase + EMAC_CTL_REG);
261 reg_val = readl(db->membase + EMAC_RX_CTL_REG);
263 writel(reg_val, db->membase + EMAC_RX_CTL_REG);
266 reg_val = readl(db->membase
[all...]
/linux-master/drivers/tty/serial/8250/
H A D8250_ioc3.c26 return readb(p->membase + (offset ^ 3));
31 writeb(value, p->membase + (offset ^ 3));
39 void __iomem *membase; local
50 membase = devm_ioremap(&pdev->dev, r->start, resource_size(r));
51 if (!membase)
66 up.port.membase = membase;
H A D8250_dwlib.h61 return ioread32be(p->membase + offset);
62 return readl(p->membase + offset);
68 iowrite32be(reg, p->membase + offset);
70 writel(reg, p->membase + offset);
H A D8250_early.c42 return readb(port->membase + offset);
44 return readw(port->membase + offset);
46 return readl(port->membase + offset);
48 return ioread32be(port->membase + offset);
62 writeb(value, port->membase + offset);
65 writew(value, port->membase + offset);
68 writel(value, port->membase + offset);
71 iowrite32be(value, port->membase + offset);
150 if (!(device->port.membase || device->port.iobase))
181 if (!(device->port.membase || devic
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/linux-master/drivers/atm/
H A Didt77252.h355 void __iomem *membase; /* SAR's memory base address */ member in struct:idt77252_dev
441 #define SAR_REG_DR0 (card->membase + 0x00)
442 #define SAR_REG_DR1 (card->membase + 0x04)
443 #define SAR_REG_DR2 (card->membase + 0x08)
444 #define SAR_REG_DR3 (card->membase + 0x0C)
445 #define SAR_REG_CMD (card->membase + 0x10)
446 #define SAR_REG_CFG (card->membase + 0x14)
447 #define SAR_REG_STAT (card->membase + 0x18)
448 #define SAR_REG_RSQB (card->membase + 0x1C)
449 #define SAR_REG_RSQT (card->membase
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/linux-master/drivers/gpio/
H A Dgpio-sa1100.c19 void __iomem *membase; member in struct:sa1100_gpio_chip
42 return readl_relaxed(sa1100_gpio_chip(chip)->membase + R_GPLR) &
50 writel_relaxed(BIT(offset), sa1100_gpio_chip(chip)->membase + reg);
55 void __iomem *gpdr = sa1100_gpio_chip(chip)->membase + R_GPDR;
65 void __iomem *gpdr = sa1100_gpio_chip(chip)->membase + R_GPDR;
77 void __iomem *gpdr = sa1100_gpio_chip(chip)->membase + R_GPDR;
105 .membase = (void *)&GPLR,
116 void *base = sgc->membase;
158 writel_relaxed(BIT(d->hwirq), sgc->membase + R_GEDR);
234 void __iomem *gedr = sgc->membase
[all...]
H A Dgpio-timberdale.c35 void __iomem *membase; member in struct:timbgpio
50 reg = ioread32(tgpio->membase + offset);
57 iowrite32(reg, tgpio->membase + offset);
73 value = ioread32(tgpio->membase + TGPIOVAL);
110 iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER);
122 iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER);
138 ver = ioread32(tgpio->membase + TGPIO_VER);
142 lvr = ioread32(tgpio->membase + TGPIO_LVR);
143 flr = ioread32(tgpio->membase + TGPIO_FLR);
145 bflr = ioread32(tgpio->membase
[all...]
/linux-master/include/uapi/linux/
H A Dkernelcapi.h28 unsigned int membase; member in struct:kcapi_carddef
/linux-master/include/linux/reset/
H A Dreset-simple.h22 * @membase: memory mapped I/O register range
39 void __iomem *membase; member in struct:reset_simple_data
/linux-master/drivers/clk/hisilicon/
H A Dreset.c22 void __iomem *membase; member in struct:hisi_reset_controller
56 reg = readl(rstc->membase + offset);
57 writel(reg | BIT(bit), rstc->membase + offset);
77 reg = readl(rstc->membase + offset);
78 writel(reg & ~BIT(bit), rstc->membase + offset);
98 rstc->membase = devm_platform_ioremap_resource(pdev, 0);
99 if (IS_ERR(rstc->membase))
/linux-master/drivers/reset/
H A Dreset-simple.c42 reg = readl(data->membase + (bank * reg_width));
47 writel(reg, data->membase + (bank * reg_width));
93 reg = readl(data->membase + (bank * reg_width));
164 void __iomem *membase; local
174 membase = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
175 if (IS_ERR(membase))
176 return PTR_ERR(membase);
179 data->membase = membase;
193 data->membase
[all...]
/linux-master/drivers/clk/x86/
H A Dclk-cgu-pll.c45 mult = lgm_get_clk_val(pll->membase, PLL_REF_DIV(pll->reg), 0, 12);
46 div = lgm_get_clk_val(pll->membase, PLL_REF_DIV(pll->reg), 18, 6);
47 frac = lgm_get_clk_val(pll->membase, pll->reg, 2, 24);
60 ret = lgm_get_clk_val(pll->membase, pll->reg, 0, 1);
71 lgm_set_clk_val(pll->membase, pll->reg, 0, 1, 1);
72 ret = regmap_read_poll_timeout_atomic(pll->membase, pll->reg,
83 lgm_set_clk_val(pll->membase, pll->reg, 0, 1, 0);
113 pll->membase = ctx->membase;

Completed in 377 milliseconds

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