tty/serial/qcom_geni_serial.c

193 	uport->membase = devm_platform_ioremap_resource(pdev, 0);
194 	if (IS_ERR(uport->membase))
195 		return PTR_ERR(uport->membase);
196 	port->se.base = uport->membase;
216 		geni_ios = readl(uport->membase + SE_GENI_IOS);
238 	writel(uart_manual_rfr, uport->membase + SE_UART_MANUAL_RFR);
260 	return readl(uport->membase + SE_GENI_STATUS) & M_GENI_CMD_ACTIVE;
265 	return readl(uport->membase + SE_GENI_STATUS) & S_GENI_CMD_ACTIVE;
297 		reg = readl(uport->membase + offset);
310 	writel(xmit_size, uport->membase + SE_UART_TX_TRANS_LEN);
312 	writel(m_cmd, uport->membase + SE_GENI_M_CMD0);
323 		writel(M_GENI_CMD_ABORT, uport->membase +
329 	writel(irq_clear, uport->membase + SE_GENI_M_IRQ_CLEAR);
336 	writel(S_GENI_CMD_ABORT, uport->membase + SE_GENI_S_CMD_CTRL_REG);
339 	writel(irq_clear, uport->membase + SE_GENI_S_IRQ_CLEAR);
340 	writel(FORCE_DEFAULT, uport->membase + GENI_FORCE_DEFAULT_REG);
352 		status = readl(uport->membase + SE_GENI_M_IRQ_STATUS);
353 		writel(status, uport->membase + SE_GENI_M_IRQ_CLEAR);
355 		status = readl(uport->membase + SE_GENI_S_IRQ_STATUS);
356 		writel(status, uport->membase + SE_GENI_S_IRQ_CLEAR);
358 		status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS);
376 			readl(uport->membase + SE_GENI_RX_FIFOn);
389 	writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
393 	writel(c, uport->membase + SE_GENI_TX_FIFOn);
394 	writel(M_TX_FIFO_WATERMARK_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
410 		       uport->membase + SE_GENI_TX_FIFOn);
433 	writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
451 		writel(M_TX_FIFO_WATERMARK_EN, uport->membase +
460 		       uport->membase + SE_GENI_TX_FIFOn);
489 	geni_status = readl(uport->membase + SE_GENI_STATUS);
509 			irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
511 					uport->membase + SE_GENI_M_IRQ_EN);
537 		ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, buf, 1);
586 	return !readl(uport->membase + SE_GENI_TX_FIFO_STATUS);
614 		writel(M_CMD_ABORT_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
617 	writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
656 	irq_en = readl(uport->membase +	SE_GENI_M_IRQ_EN);
659 	writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
660 	writel(irq_en, uport->membase +	SE_GENI_M_IRQ_EN);
668 	irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
670 	writel(0, uport->membase + SE_GENI_TX_WATERMARK_REG);
671 	writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
682 		writel(M_CMD_ABORT_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
684 	writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
695 	status = readl(uport->membase +	SE_GENI_RX_FIFO_STATUS);
717 	irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN);
719 	writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN);
721 	irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
723 	writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
735 	s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS);
739 	writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR);
755 	irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN);
757 	writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN);
759 	irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
761 	writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
819 	rx_in = readl(uport->membase + SE_DMA_RX_LEN_IN);
869 		iowrite32_rep(uport->membase + SE_GENI_TX_FIFOn, buf, 1);
887 	status = readl(uport->membase + SE_GENI_TX_FIFO_STATUS);
912 		irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
915 					uport->membase + SE_GENI_M_IRQ_EN);
926 			uport->membase + SE_GENI_M_IRQ_CLEAR);
930 		irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
933 					uport->membase + SE_GENI_M_IRQ_EN);
976 	m_irq_status = readl(uport->membase + SE_GENI_M_IRQ_STATUS);
977 	s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS);
978 	dma_tx_status = readl(uport->membase + SE_DMA_TX_IRQ_STAT);
979 	dma_rx_status = readl(uport->membase + SE_DMA_RX_IRQ_STAT);
980 	geni_status = readl(uport->membase + SE_GENI_STATUS);
981 	dma = readl(uport->membase + SE_GENI_DMA_MODE_EN);
982 	m_irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
983 	writel(m_irq_status, uport->membase + SE_GENI_M_IRQ_CLEAR);
984 	writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR);
985 	writel(dma_tx_status, uport->membase + SE_DMA_TX_IRQ_CLR);
986 	writel(dma_rx_status, uport->membase + SE_DMA_RX_IRQ_CLR);
1101 	writel(rxstale, uport->membase + SE_UART_RX_STALE_CNT);
1103 	pin_swap = readl(uport->membase + SE_UART_IO_MACRO_CTRL);
1114 		writel(pin_swap, uport->membase + SE_UART_IO_MACRO_CTRL);
1266 	tx_trans_cfg = readl(uport->membase + SE_UART_TX_TRANS_CFG);
1267 	tx_parity_cfg = readl(uport->membase + SE_UART_TX_PARITY_CFG);
1268 	rx_trans_cfg = readl(uport->membase + SE_UART_RX_TRANS_CFG);
1269 	rx_parity_cfg = readl(uport->membase + SE_UART_RX_PARITY_CFG);
1312 				uport->membase + SE_UART_LOOPBACK_CFG);
1313 	writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG);
1314 	writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG);
1315 	writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG);
1316 	writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG);
1317 	writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN);
1318 	writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN);
1319 	writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN);
1320 	writel(ser_clk_cfg, uport->membase + GENI_SER_M_CLK_CFG);
1321 	writel(ser_clk_cfg, uport->membase + GENI_SER_S_CLK_CFG);
1348 	if (unlikely(!uport->membase))
1415 	if (!uport->membase)
1421 	se.base = uport->membase;
1442 	writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG);
1443 	writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG);
1444 	writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG);
1445 	writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG);
1446 	writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN);
1447 	writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN);
1448 	writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN);