1178479Sjb/* SPDX-License-Identifier: GPL-2.0-or-later */ 2178479Sjb/* 3178479Sjb * Simple Reset Controller ops 4178479Sjb * 5178479Sjb * Based on Allwinner SoCs Reset Controller driver 6178479Sjb * 7178479Sjb * Copyright 2013 Maxime Ripard 8178479Sjb * 9178479Sjb * Maxime Ripard <maxime.ripard@free-electrons.com> 10178479Sjb */ 11178479Sjb 12178479Sjb#ifndef __RESET_SIMPLE_H__ 13178479Sjb#define __RESET_SIMPLE_H__ 14178479Sjb 15178479Sjb#include <linux/io.h> 16178479Sjb#include <linux/reset-controller.h> 17178479Sjb#include <linux/spinlock.h> 18178479Sjb 19178479Sjb/** 20178479Sjb * struct reset_simple_data - driver data for simple reset controllers 21178479Sjb * @lock: spinlock to protect registers during read-modify-write cycles 22178479Sjb * @membase: memory mapped I/O register range 23178479Sjb * @rcdev: reset controller device base structure 24178479Sjb * @active_low: if true, bits are cleared to assert the reset. Otherwise, bits 25178479Sjb * are set to assert the reset. Note that this says nothing about 26268578Srpaulo * the voltage level of the actual reset line. 27268578Srpaulo * @status_active_low: if true, bits read back as cleared while the reset is 28268578Srpaulo * asserted. Otherwise, bits read back as set while the 29268578Srpaulo * reset is asserted. 30178479Sjb * @reset_us: Minimum delay in microseconds needed that needs to be 31178479Sjb * waited for between an assert and a deassert to reset the 32178479Sjb * device. If multiple consumers with different delay 33178479Sjb * requirements are connected to this controller, it must 34178479Sjb * be the largest minimum delay. 0 means that such a delay is 35178479Sjb * unknown and the reset operation is unsupported. 36178479Sjb */ 37178479Sjbstruct reset_simple_data { 38178479Sjb spinlock_t lock; 39178479Sjb void __iomem *membase; 40178479Sjb struct reset_controller_dev rcdev; 41178479Sjb bool active_low; 42178479Sjb bool status_active_low; 43178479Sjb unsigned int reset_us; 44178479Sjb}; 45178479Sjb 46178479Sjbextern const struct reset_control_ops reset_simple_ops; 47178479Sjb 48178479Sjb#endif /* __RESET_SIMPLE_H__ */ 49178479Sjb