tty/serial/milbeaut_usio.c

67 	writew(readw(port->membase + MLB_USIO_REG_FCR) & ~MLB_USIO_FCR_FTIE,
68 	       port->membase + MLB_USIO_REG_FCR);
69 	writeb(readb(port->membase + MLB_USIO_REG_SCR) & ~MLB_USIO_SCR_TBIE,
70 	       port->membase + MLB_USIO_REG_SCR);
78 	writew(readw(port->membase + MLB_USIO_REG_FCR) & ~MLB_USIO_FCR_FTIE,
79 	       port->membase + MLB_USIO_REG_FCR);
80 	writeb(readb(port->membase + MLB_USIO_REG_SCR) &
82 	       port->membase + MLB_USIO_REG_SCR);
85 		writew(port->x_char, port->membase + MLB_USIO_REG_DR);
96 		(readw(port->membase + MLB_USIO_REG_FBYTE) & 0xff);
99 		writew(xmit->buf[xmit->tail], port->membase + MLB_USIO_REG_DR);
107 	writew(readw(port->membase + MLB_USIO_REG_FCR) & ~MLB_USIO_FCR_FDRQ,
108 	       port->membase + MLB_USIO_REG_FCR);
110 	writeb(readb(port->membase + MLB_USIO_REG_SCR) | MLB_USIO_SCR_TBIE,
111 	       port->membase + MLB_USIO_REG_SCR);
122 	u16 fcr = readw(port->membase + MLB_USIO_REG_FCR);
124 	writew(fcr | MLB_USIO_FCR_FTIE, port->membase + MLB_USIO_REG_FCR);
128 	writeb(readb(port->membase + MLB_USIO_REG_SCR) | MLB_USIO_SCR_TBIE,
129 	       port->membase + MLB_USIO_REG_SCR);
131 	if (readb(port->membase + MLB_USIO_REG_SSR) & MLB_USIO_SSR_TBI)
137 	writeb(readb(port->membase + MLB_USIO_REG_SCR) & ~MLB_USIO_SCR_RIE,
138 	       port->membase + MLB_USIO_REG_SCR);
143 	writeb(readb(port->membase + MLB_USIO_REG_SCR) |
145 	       port->membase + MLB_USIO_REG_SCR);
156 		status = readb(port->membase + MLB_USIO_REG_SSR);
163 			ch = readw(port->membase + MLB_USIO_REG_DR);
193 		writeb(readb(port->membase + MLB_USIO_REG_SSR) |
195 				port->membase + MLB_USIO_REG_SSR);
197 		max_count = readw(port->membase + MLB_USIO_REG_FBYTE) >> 8;
198 		writew(readw(port->membase + MLB_USIO_REG_FCR) |
200 		port->membase + MLB_USIO_REG_FCR);
222 	if (readb(port->membase + MLB_USIO_REG_SSR) & MLB_USIO_SSR_TBI)
231 	return (readb(port->membase + MLB_USIO_REG_SSR) & MLB_USIO_SSR_TBI) ?
267 	escr = readb(port->membase + MLB_USIO_REG_ESCR);
271 	writeb(0, port->membase + MLB_USIO_REG_SCR);
272 	writeb(escr, port->membase + MLB_USIO_REG_ESCR);
273 	writeb(MLB_USIO_SCR_UPCL, port->membase + MLB_USIO_REG_SCR);
274 	writeb(MLB_USIO_SSR_REC, port->membase + MLB_USIO_REG_SSR);
275 	writew(0, port->membase + MLB_USIO_REG_FCR);
277 	       port->membase + MLB_USIO_REG_FCR);
279 	       port->membase + MLB_USIO_REG_FCR);
280 	writew(0, port->membase + MLB_USIO_REG_FBYTE);
281 	writew(BIT(12), port->membase + MLB_USIO_REG_FBYTE);
284 	       MLB_USIO_SCR_RXE, port->membase + MLB_USIO_REG_SCR);
355 	writeb(0, port->membase + MLB_USIO_REG_SCR);
356 	writeb(MLB_USIO_SCR_UPCL, port->membase + MLB_USIO_REG_SCR);
357 	writeb(MLB_USIO_SSR_REC, port->membase + MLB_USIO_REG_SSR);
358 	writew(0, port->membase + MLB_USIO_REG_FCR);
359 	writeb(smr, port->membase + MLB_USIO_REG_SMR);
360 	writeb(escr, port->membase + MLB_USIO_REG_ESCR);
361 	writew(quot, port->membase + MLB_USIO_REG_BGR);
362 	writew(0, port->membase + MLB_USIO_REG_FCR);
365 	       port->membase + MLB_USIO_REG_FCR);
366 	writew(0, port->membase + MLB_USIO_REG_FBYTE);
367 	writew(BIT(12), port->membase + MLB_USIO_REG_FBYTE);
369 	       MLB_USIO_SCR_TXE, port->membase + MLB_USIO_REG_SCR);
404 	while (!(readb(port->membase + MLB_USIO_REG_SSR) & MLB_USIO_SSR_TDRE))
407 	writew(c, port->membase + MLB_USIO_REG_DR);
430 	if (!port->membase)
474 	if (!device->port.membase)
523 	port->membase = devm_ioremap(&pdev->dev, res->start,