Searched refs:mdp4_write (Results 1 - 9 of 9) sorted by relevance

/linux-master/drivers/gpu/drm/msm/disp/mdp4/
H A Dmdp4_dsi_encoder.c59 mdp4_write(mdp4_kms, REG_MDP4_DSI_HSYNC_CTRL,
62 mdp4_write(mdp4_kms, REG_MDP4_DSI_VSYNC_PERIOD, vsync_period);
63 mdp4_write(mdp4_kms, REG_MDP4_DSI_VSYNC_LEN, vsync_len);
64 mdp4_write(mdp4_kms, REG_MDP4_DSI_DISPLAY_HCTRL,
67 mdp4_write(mdp4_kms, REG_MDP4_DSI_DISPLAY_VSTART, display_v_start);
68 mdp4_write(mdp4_kms, REG_MDP4_DSI_DISPLAY_VEND, display_v_end);
70 mdp4_write(mdp4_kms, REG_MDP4_DSI_CTRL_POLARITY, ctrl_pol);
71 mdp4_write(mdp4_kms, REG_MDP4_DSI_UNDERFLOW_CLR,
74 mdp4_write(mdp4_kms, REG_MDP4_DSI_ACTIVE_HCTL,
77 mdp4_write(mdp4_km
[all...]
H A Dmdp4_lcdc_encoder.c68 mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(0),
73 mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(0),
77 mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(1),
82 mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(1),
86 mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(2),
91 mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(2),
95 mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(3),
100 mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(3),
122 mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(0),
127 mdp4_write(mdp4_km
[all...]
H A Dmdp4_dtv_encoder.c63 mdp4_write(mdp4_kms, REG_MDP4_DTV_HSYNC_CTRL,
66 mdp4_write(mdp4_kms, REG_MDP4_DTV_VSYNC_PERIOD, vsync_period);
67 mdp4_write(mdp4_kms, REG_MDP4_DTV_VSYNC_LEN, vsync_len);
68 mdp4_write(mdp4_kms, REG_MDP4_DTV_DISPLAY_HCTRL,
71 mdp4_write(mdp4_kms, REG_MDP4_DTV_DISPLAY_VSTART, display_v_start);
72 mdp4_write(mdp4_kms, REG_MDP4_DTV_DISPLAY_VEND, display_v_end);
73 mdp4_write(mdp4_kms, REG_MDP4_DTV_BORDER_CLR, 0);
74 mdp4_write(mdp4_kms, REG_MDP4_DTV_UNDERFLOW_CLR,
77 mdp4_write(mdp4_kms, REG_MDP4_DTV_HSYNC_SKEW, dtv_hsync_skew);
78 mdp4_write(mdp4_km
[all...]
H A Dmdp4_irq.c16 mdp4_write(to_mdp4_kms(mdp_kms), REG_MDP4_INTR_CLEAR,
18 mdp4_write(to_mdp4_kms(mdp_kms), REG_MDP4_INTR_ENABLE, irqmask);
39 mdp4_write(mdp4_kms, REG_MDP4_INTR_CLEAR, 0xffffffff);
40 mdp4_write(mdp4_kms, REG_MDP4_INTR_ENABLE, 0x00000000);
63 mdp4_write(mdp4_kms, REG_MDP4_INTR_ENABLE, 0x00000000);
77 mdp4_write(mdp4_kms, REG_MDP4_INTR_CLEAR, status);
H A Dmdp4_crtc.c95 mdp4_write(mdp4_kms, REG_MDP4_OVERLAY_FLUSH, flush);
165 mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG, mixer_cfg);
176 mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_LOW0(ovlp), 0);
177 mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_LOW1(ovlp), 0);
178 mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_HIGH0(ovlp), 0);
179 mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_HIGH1(ovlp), 0);
203 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_FG_ALPHA(ovlp, i), 0xff);
204 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_BG_ALPHA(ovlp, i), 0x00);
205 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_OP(ovlp, i), op);
206 mdp4_write(mdp4_km
[all...]
H A Dmdp4_plane.c163 mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRC_STRIDE_A(pipe),
167 mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRC_STRIDE_B(pipe),
171 mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRCP0_BASE(pipe),
173 mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRCP1_BASE(pipe),
175 mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRCP2_BASE(pipe),
177 mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRCP3_BASE(pipe),
187 mdp4_write(mdp4_kms, REG_MDP4_PIPE_CSC_MV(pipe, i),
192 mdp4_write(mdp4_kms, REG_MDP4_PIPE_CSC_PRE_BV(pipe, i),
195 mdp4_write(mdp4_kms, REG_MDP4_PIPE_CSC_POST_BV(pipe, i),
200 mdp4_write(mdp4_km
[all...]
H A Dmdp4_kms.c26 mdp4_write(mdp4_kms, REG_MDP4_CS_CONTROLLER0, 0x0707ffff);
27 mdp4_write(mdp4_kms, REG_MDP4_CS_CONTROLLER1, 0x03073f3f);
30 mdp4_write(mdp4_kms, REG_MDP4_PORTMAP_MODE, 0x3);
33 mdp4_write(mdp4_kms, REG_MDP4_READ_CNFG, 0x02222);
47 mdp4_write(mdp4_kms, REG_MDP4_DMA_FETCH_CONFIG(DMA_P), dmap_cfg);
48 mdp4_write(mdp4_kms, REG_MDP4_DMA_FETCH_CONFIG(DMA_E), dmap_cfg);
50 mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(VG1), vg_cfg);
51 mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(VG2), vg_cfg);
52 mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(RGB1), vg_cfg);
53 mdp4_write(mdp4_km
[all...]
H A Dmdp4_lvds_pll.c69 mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_PHY_RESET, 0x33);
72 mdp4_write(mdp4_kms, pll_rate->conf[i].reg, pll_rate->conf[i].val);
74 mdp4_write(mdp4_kms, REG_MDP4_LVDS_PHY_PLL_CTRL_0, 0x01);
90 mdp4_write(mdp4_kms, REG_MDP4_LVDS_PHY_CFG0, 0x0);
91 mdp4_write(mdp4_kms, REG_MDP4_LVDS_PHY_PLL_CTRL_0, 0x0);
H A Dmdp4_kms.h45 static inline void mdp4_write(struct mdp4_kms *mdp4_kms, u32 reg, u32 data) function

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