Lines Matching refs:mdp4_write
63 mdp4_write(mdp4_kms, REG_MDP4_DTV_HSYNC_CTRL,
66 mdp4_write(mdp4_kms, REG_MDP4_DTV_VSYNC_PERIOD, vsync_period);
67 mdp4_write(mdp4_kms, REG_MDP4_DTV_VSYNC_LEN, vsync_len);
68 mdp4_write(mdp4_kms, REG_MDP4_DTV_DISPLAY_HCTRL,
71 mdp4_write(mdp4_kms, REG_MDP4_DTV_DISPLAY_VSTART, display_v_start);
72 mdp4_write(mdp4_kms, REG_MDP4_DTV_DISPLAY_VEND, display_v_end);
73 mdp4_write(mdp4_kms, REG_MDP4_DTV_BORDER_CLR, 0);
74 mdp4_write(mdp4_kms, REG_MDP4_DTV_UNDERFLOW_CLR,
77 mdp4_write(mdp4_kms, REG_MDP4_DTV_HSYNC_SKEW, dtv_hsync_skew);
78 mdp4_write(mdp4_kms, REG_MDP4_DTV_CTRL_POLARITY, ctrl_pol);
79 mdp4_write(mdp4_kms, REG_MDP4_DTV_ACTIVE_HCTL,
82 mdp4_write(mdp4_kms, REG_MDP4_DTV_ACTIVE_VSTART, 0);
83 mdp4_write(mdp4_kms, REG_MDP4_DTV_ACTIVE_VEND, 0);
94 mdp4_write(mdp4_kms, REG_MDP4_DTV_ENABLE, 0);
145 mdp4_write(mdp4_kms, REG_MDP4_DTV_ENABLE, 1);