1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (C) 2013 Red Hat 4 * Author: Rob Clark <robdclark@gmail.com> 5 */ 6 7#include <drm/drm_crtc.h> 8#include <drm/drm_probe_helper.h> 9 10#include "mdp4_kms.h" 11 12struct mdp4_dtv_encoder { 13 struct drm_encoder base; 14 struct clk *hdmi_clk; 15 struct clk *mdp_clk; 16 unsigned long int pixclock; 17 bool enabled; 18 uint32_t bsc; 19}; 20#define to_mdp4_dtv_encoder(x) container_of(x, struct mdp4_dtv_encoder, base) 21 22static struct mdp4_kms *get_kms(struct drm_encoder *encoder) 23{ 24 struct msm_drm_private *priv = encoder->dev->dev_private; 25 return to_mdp4_kms(to_mdp_kms(priv->kms)); 26} 27 28static void mdp4_dtv_encoder_mode_set(struct drm_encoder *encoder, 29 struct drm_display_mode *mode, 30 struct drm_display_mode *adjusted_mode) 31{ 32 struct mdp4_dtv_encoder *mdp4_dtv_encoder = to_mdp4_dtv_encoder(encoder); 33 struct mdp4_kms *mdp4_kms = get_kms(encoder); 34 uint32_t dtv_hsync_skew, vsync_period, vsync_len, ctrl_pol; 35 uint32_t display_v_start, display_v_end; 36 uint32_t hsync_start_x, hsync_end_x; 37 38 mode = adjusted_mode; 39 40 DBG("set mode: " DRM_MODE_FMT, DRM_MODE_ARG(mode)); 41 42 mdp4_dtv_encoder->pixclock = mode->clock * 1000; 43 44 DBG("pixclock=%lu", mdp4_dtv_encoder->pixclock); 45 46 ctrl_pol = 0; 47 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 48 ctrl_pol |= MDP4_DTV_CTRL_POLARITY_HSYNC_LOW; 49 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 50 ctrl_pol |= MDP4_DTV_CTRL_POLARITY_VSYNC_LOW; 51 /* probably need to get DATA_EN polarity from panel.. */ 52 53 dtv_hsync_skew = 0; /* get this from panel? */ 54 55 hsync_start_x = (mode->htotal - mode->hsync_start); 56 hsync_end_x = mode->htotal - (mode->hsync_start - mode->hdisplay) - 1; 57 58 vsync_period = mode->vtotal * mode->htotal; 59 vsync_len = (mode->vsync_end - mode->vsync_start) * mode->htotal; 60 display_v_start = (mode->vtotal - mode->vsync_start) * mode->htotal + dtv_hsync_skew; 61 display_v_end = vsync_period - ((mode->vsync_start - mode->vdisplay) * mode->htotal) + dtv_hsync_skew - 1; 62 63 mdp4_write(mdp4_kms, REG_MDP4_DTV_HSYNC_CTRL, 64 MDP4_DTV_HSYNC_CTRL_PULSEW(mode->hsync_end - mode->hsync_start) | 65 MDP4_DTV_HSYNC_CTRL_PERIOD(mode->htotal)); 66 mdp4_write(mdp4_kms, REG_MDP4_DTV_VSYNC_PERIOD, vsync_period); 67 mdp4_write(mdp4_kms, REG_MDP4_DTV_VSYNC_LEN, vsync_len); 68 mdp4_write(mdp4_kms, REG_MDP4_DTV_DISPLAY_HCTRL, 69 MDP4_DTV_DISPLAY_HCTRL_START(hsync_start_x) | 70 MDP4_DTV_DISPLAY_HCTRL_END(hsync_end_x)); 71 mdp4_write(mdp4_kms, REG_MDP4_DTV_DISPLAY_VSTART, display_v_start); 72 mdp4_write(mdp4_kms, REG_MDP4_DTV_DISPLAY_VEND, display_v_end); 73 mdp4_write(mdp4_kms, REG_MDP4_DTV_BORDER_CLR, 0); 74 mdp4_write(mdp4_kms, REG_MDP4_DTV_UNDERFLOW_CLR, 75 MDP4_DTV_UNDERFLOW_CLR_ENABLE_RECOVERY | 76 MDP4_DTV_UNDERFLOW_CLR_COLOR(0xff)); 77 mdp4_write(mdp4_kms, REG_MDP4_DTV_HSYNC_SKEW, dtv_hsync_skew); 78 mdp4_write(mdp4_kms, REG_MDP4_DTV_CTRL_POLARITY, ctrl_pol); 79 mdp4_write(mdp4_kms, REG_MDP4_DTV_ACTIVE_HCTL, 80 MDP4_DTV_ACTIVE_HCTL_START(0) | 81 MDP4_DTV_ACTIVE_HCTL_END(0)); 82 mdp4_write(mdp4_kms, REG_MDP4_DTV_ACTIVE_VSTART, 0); 83 mdp4_write(mdp4_kms, REG_MDP4_DTV_ACTIVE_VEND, 0); 84} 85 86static void mdp4_dtv_encoder_disable(struct drm_encoder *encoder) 87{ 88 struct mdp4_dtv_encoder *mdp4_dtv_encoder = to_mdp4_dtv_encoder(encoder); 89 struct mdp4_kms *mdp4_kms = get_kms(encoder); 90 91 if (WARN_ON(!mdp4_dtv_encoder->enabled)) 92 return; 93 94 mdp4_write(mdp4_kms, REG_MDP4_DTV_ENABLE, 0); 95 96 /* 97 * Wait for a vsync so we know the ENABLE=0 latched before 98 * the (connector) source of the vsync's gets disabled, 99 * otherwise we end up in a funny state if we re-enable 100 * before the disable latches, which results that some of 101 * the settings changes for the new modeset (like new 102 * scanout buffer) don't latch properly.. 103 */ 104 mdp_irq_wait(&mdp4_kms->base, MDP4_IRQ_EXTERNAL_VSYNC); 105 106 clk_disable_unprepare(mdp4_dtv_encoder->hdmi_clk); 107 clk_disable_unprepare(mdp4_dtv_encoder->mdp_clk); 108 109 mdp4_dtv_encoder->enabled = false; 110} 111 112static void mdp4_dtv_encoder_enable(struct drm_encoder *encoder) 113{ 114 struct drm_device *dev = encoder->dev; 115 struct mdp4_dtv_encoder *mdp4_dtv_encoder = to_mdp4_dtv_encoder(encoder); 116 struct mdp4_kms *mdp4_kms = get_kms(encoder); 117 unsigned long pc = mdp4_dtv_encoder->pixclock; 118 int ret; 119 120 if (WARN_ON(mdp4_dtv_encoder->enabled)) 121 return; 122 123 mdp4_crtc_set_config(encoder->crtc, 124 MDP4_DMA_CONFIG_R_BPC(BPC8) | 125 MDP4_DMA_CONFIG_G_BPC(BPC8) | 126 MDP4_DMA_CONFIG_B_BPC(BPC8) | 127 MDP4_DMA_CONFIG_PACK(0x21)); 128 mdp4_crtc_set_intf(encoder->crtc, INTF_LCDC_DTV, 1); 129 130 DBG("setting mdp_clk=%lu", pc); 131 132 ret = clk_set_rate(mdp4_dtv_encoder->mdp_clk, pc); 133 if (ret) 134 DRM_DEV_ERROR(dev->dev, "failed to set mdp_clk to %lu: %d\n", 135 pc, ret); 136 137 ret = clk_prepare_enable(mdp4_dtv_encoder->mdp_clk); 138 if (ret) 139 DRM_DEV_ERROR(dev->dev, "failed to enabled mdp_clk: %d\n", ret); 140 141 ret = clk_prepare_enable(mdp4_dtv_encoder->hdmi_clk); 142 if (ret) 143 DRM_DEV_ERROR(dev->dev, "failed to enable hdmi_clk: %d\n", ret); 144 145 mdp4_write(mdp4_kms, REG_MDP4_DTV_ENABLE, 1); 146 147 mdp4_dtv_encoder->enabled = true; 148} 149 150static const struct drm_encoder_helper_funcs mdp4_dtv_encoder_helper_funcs = { 151 .mode_set = mdp4_dtv_encoder_mode_set, 152 .enable = mdp4_dtv_encoder_enable, 153 .disable = mdp4_dtv_encoder_disable, 154}; 155 156long mdp4_dtv_round_pixclk(struct drm_encoder *encoder, unsigned long rate) 157{ 158 struct mdp4_dtv_encoder *mdp4_dtv_encoder = to_mdp4_dtv_encoder(encoder); 159 return clk_round_rate(mdp4_dtv_encoder->mdp_clk, rate); 160} 161 162/* initialize encoder */ 163struct drm_encoder *mdp4_dtv_encoder_init(struct drm_device *dev) 164{ 165 struct drm_encoder *encoder; 166 struct mdp4_dtv_encoder *mdp4_dtv_encoder; 167 168 mdp4_dtv_encoder = drmm_encoder_alloc(dev, struct mdp4_dtv_encoder, base, 169 NULL, DRM_MODE_ENCODER_TMDS, NULL); 170 if (IS_ERR(mdp4_dtv_encoder)) 171 return ERR_CAST(mdp4_dtv_encoder); 172 173 encoder = &mdp4_dtv_encoder->base; 174 175 drm_encoder_helper_add(encoder, &mdp4_dtv_encoder_helper_funcs); 176 177 mdp4_dtv_encoder->hdmi_clk = devm_clk_get(dev->dev, "hdmi_clk"); 178 if (IS_ERR(mdp4_dtv_encoder->hdmi_clk)) { 179 DRM_DEV_ERROR(dev->dev, "failed to get hdmi_clk\n"); 180 return ERR_CAST(mdp4_dtv_encoder->hdmi_clk); 181 } 182 183 mdp4_dtv_encoder->mdp_clk = devm_clk_get(dev->dev, "tv_clk"); 184 if (IS_ERR(mdp4_dtv_encoder->mdp_clk)) { 185 DRM_DEV_ERROR(dev->dev, "failed to get tv_clk\n"); 186 return ERR_CAST(mdp4_dtv_encoder->mdp_clk); 187 } 188 189 return encoder; 190} 191