Lines Matching refs:mdp4_write
26 mdp4_write(mdp4_kms, REG_MDP4_CS_CONTROLLER0, 0x0707ffff);
27 mdp4_write(mdp4_kms, REG_MDP4_CS_CONTROLLER1, 0x03073f3f);
30 mdp4_write(mdp4_kms, REG_MDP4_PORTMAP_MODE, 0x3);
33 mdp4_write(mdp4_kms, REG_MDP4_READ_CNFG, 0x02222);
47 mdp4_write(mdp4_kms, REG_MDP4_DMA_FETCH_CONFIG(DMA_P), dmap_cfg);
48 mdp4_write(mdp4_kms, REG_MDP4_DMA_FETCH_CONFIG(DMA_E), dmap_cfg);
50 mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(VG1), vg_cfg);
51 mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(VG2), vg_cfg);
52 mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(RGB1), vg_cfg);
53 mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(RGB2), vg_cfg);
56 mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG_UPDATE_METHOD, 1);
57 mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG, 0);
60 mdp4_write(mdp4_kms, REG_MDP4_PIPE_OP_MODE(VG1), 0);
61 mdp4_write(mdp4_kms, REG_MDP4_PIPE_OP_MODE(VG2), 0);
62 mdp4_write(mdp4_kms, REG_MDP4_DMA_P_OP_MODE, 0);
63 mdp4_write(mdp4_kms, REG_MDP4_DMA_S_OP_MODE, 0);
64 mdp4_write(mdp4_kms, REG_MDP4_OVLP_CSC_CONFIG(1), 0);
65 mdp4_write(mdp4_kms, REG_MDP4_OVLP_CSC_CONFIG(2), 0);
68 mdp4_write(mdp4_kms, REG_MDP4_RESET_STATUS, 1);
439 mdp4_write(mdp4_kms, REG_MDP4_DTV_ENABLE, 0);
440 mdp4_write(mdp4_kms, REG_MDP4_LCDC_ENABLE, 0);
441 mdp4_write(mdp4_kms, REG_MDP4_DSI_ENABLE, 0);