Lines Matching refs:mdp4_write
59 mdp4_write(mdp4_kms, REG_MDP4_DSI_HSYNC_CTRL,
62 mdp4_write(mdp4_kms, REG_MDP4_DSI_VSYNC_PERIOD, vsync_period);
63 mdp4_write(mdp4_kms, REG_MDP4_DSI_VSYNC_LEN, vsync_len);
64 mdp4_write(mdp4_kms, REG_MDP4_DSI_DISPLAY_HCTRL,
67 mdp4_write(mdp4_kms, REG_MDP4_DSI_DISPLAY_VSTART, display_v_start);
68 mdp4_write(mdp4_kms, REG_MDP4_DSI_DISPLAY_VEND, display_v_end);
70 mdp4_write(mdp4_kms, REG_MDP4_DSI_CTRL_POLARITY, ctrl_pol);
71 mdp4_write(mdp4_kms, REG_MDP4_DSI_UNDERFLOW_CLR,
74 mdp4_write(mdp4_kms, REG_MDP4_DSI_ACTIVE_HCTL,
77 mdp4_write(mdp4_kms, REG_MDP4_DSI_HSYNC_SKEW, dsi_hsync_skew);
78 mdp4_write(mdp4_kms, REG_MDP4_DSI_BORDER_CLR, 0);
79 mdp4_write(mdp4_kms, REG_MDP4_DSI_ACTIVE_VSTART, 0);
80 mdp4_write(mdp4_kms, REG_MDP4_DSI_ACTIVE_VEND, 0);
91 mdp4_write(mdp4_kms, REG_MDP4_DSI_ENABLE, 0);
125 mdp4_write(mdp4_kms, REG_MDP4_DSI_ENABLE, 1);