Searched refs:max_dac1_clock_8 (Results 1 - 20 of 20) sorted by relevance

/haiku/src/add-ons/accelerants/neomagic/engine/
H A Dnm_info.c19 si->ps.max_dac1_clock_8 = 65;
39 si->ps.max_dac1_clock_8 = 80;
58 si->ps.max_dac1_clock_8 = 80;
77 si->ps.max_dac1_clock_8 = 90;
96 si->ps.max_dac1_clock_8 = 110;
115 si->ps.max_dac1_clock_8 = 110;
134 si->ps.max_dac1_clock_8 = 110;
153 si->ps.max_dac1_clock_8 = 110;
246 LOG(2,("max_dac1_clock_8: %dMhz\n", si->ps.max_dac1_clock_8));
[all...]
H A Dnm_dac.c239 max_pclk = si->ps.max_dac1_clock_8;
/haiku/src/add-ons/accelerants/matrox/engine/
H A Dmga_info.c172 si->ps.max_dac1_clock_8 = (pins[31] << 8) | pins[30];//4mb
208 si->ps.max_dac1_clock_8 = pins[37] + 100;
290 si->ps.max_dac1_clock = si->ps.max_dac1_clock_8;
337 if (pins[40] == 0xff) si->ps.max_dac1_clock_8 = si->ps.max_pixel_vco;
338 else si->ps.max_dac1_clock_8 = 4 * pins[40];
340 if (pins[41] == 0xff) si->ps.max_dac1_clock_16 = si->ps.max_dac1_clock_8;
426 si->ps.max_dac1_clock = si->ps.max_dac1_clock_8;
481 if (pins[39] == 0xff) si->ps.max_dac1_clock_8 = si->ps.max_pixel_vco;
482 else si->ps.max_dac1_clock_8 = 4 * pins[39];
484 if (pins[40] == 0xff) si->ps.max_dac1_clock_16 = si->ps.max_dac1_clock_8;
[all...]
H A Dmga_dac.c358 max_pclk = si->ps.max_dac1_clock_8;
505 max_pclk = si->ps.max_dac1_clock_8;
639 max_pclk = si->ps.max_dac1_clock_8;
/haiku/src/add-ons/accelerants/neomagic/
H A DGetModeInfo.c59 max_pclk = si->ps.max_dac1_clock_8;
/haiku/src/add-ons/accelerants/matrox/
H A DGetModeInfo.c110 max_pclk = si->ps.max_dac1_clock_8;
/haiku/src/add-ons/accelerants/skeleton/
H A DGetModeInfo.c102 max_pclk = si->ps.max_dac1_clock_8;
/haiku/src/add-ons/accelerants/via/
H A DGetModeInfo.c102 max_pclk = si->ps.max_dac1_clock_8;
/haiku/src/add-ons/accelerants/nvidia/
H A DGetModeInfo.c102 max_pclk = si->ps.max_dac1_clock_8;
/haiku/src/add-ons/accelerants/via/engine/
H A Dinfo.c692 si->ps.max_dac1_clock_8 = 230;
726 si->ps.max_dac1_clock_8 = 300;
760 si->ps.max_dac1_clock_8 = 300;
794 si->ps.max_dac1_clock_8 = 350;
846 si->ps.max_dac1_clock_8 = 350;
896 si->ps.max_dac1_clock_8 = 350;
1049 LOG(2,("max_dac1_clock_8: %dMhz\n", si->ps.max_dac1_clock_8));
H A Ddac.c285 max_pclk = si->ps.max_dac1_clock_8;
432 max_pclk = si->ps.max_dac1_clock_8;
/haiku/headers/private/graphics/matrox/
H A DDriverInterface.h212 uint32 max_dac1_clock_8; /* dac1 limits correlated to RAMspeed limits (Mhz) */ member in struct:__anon785::__anon789
/haiku/headers/private/graphics/neomagic/
H A DDriverInterface.h199 uint32 max_dac1_clock_8; /* dac1 limits correlated to RAMspeed limits (Mhz) */ member in struct:__anon799::__anon803
/haiku/headers/private/graphics/skeleton/
H A DDriverInterface.h266 uint32 max_dac1_clock_8; /* dac1 limits correlated to RAMspeed limits (Mhz) */ member in struct:__anon937::__anon943
/haiku/headers/private/graphics/via/
H A DDriverInterface.h277 uint32 max_dac1_clock_8; /* dac1 limits correlated to RAMspeed limits (Mhz) */ member in struct:__anon7::__anon10
/haiku/headers/private/graphics/nvidia/
H A DDriverInterface.h406 uint32 max_dac1_clock_8; /* dac1 limits correlated to RAMspeed limits (Mhz) */ member in struct:__anon21::__anon27
/haiku/src/add-ons/accelerants/skeleton/engine/
H A Dinfo.c2623 si->ps.max_dac1_clock_8 = 250;
2657 si->ps.max_dac1_clock_8 = 300;
2691 si->ps.max_dac1_clock_8 = 300;
2725 si->ps.max_dac1_clock_8 = 350;
2777 si->ps.max_dac1_clock_8 = 350;
2827 si->ps.max_dac1_clock_8 = 350;
3032 LOG(2,("max_dac1_clock_8: %dMhz\n", si->ps.max_dac1_clock_8));
H A Ddac.c253 max_pclk = si->ps.max_dac1_clock_8;
/haiku/src/add-ons/accelerants/nvidia/engine/
H A Dnv_info.c2979 si->ps.max_dac1_clock_8 = 250;
3013 si->ps.max_dac1_clock_8 = 300;
3047 si->ps.max_dac1_clock_8 = 300;
3081 si->ps.max_dac1_clock_8 = 350;
3133 si->ps.max_dac1_clock_8 = 350;
3198 si->ps.max_dac1_clock_8 = 350;
3376 LOG(2,("max_dac1_clock_8: %dMhz\n", si->ps.max_dac1_clock_8));
H A Dnv_dac.c344 max_pclk = si->ps.max_dac1_clock_8;

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