1/* 2 Copyright 1999, Be Incorporated. All Rights Reserved. 3 This file may be used under the terms of the Be Sample Code License. 4 5 Other authors: 6 Mark Watson; 7 Apsed; 8 Rudolf Cornelissen 10/2002-1/2016. 9*/ 10 11#ifndef DRIVERINTERFACE_H 12#define DRIVERINTERFACE_H 13 14#include <Accelerant.h> 15#include <video_overlay.h> 16#include <Drivers.h> 17#include <PCI.h> 18#include <OS.h> 19#include <edid.h> 20#include <AGP.h> 21 22#define DRIVER_PREFIX "nvidia" 23#define DEVICE_FORMAT "%04x_%04x_%02x%02x%02x" 24 25/* 26 Internal driver state (also for sharing info between driver and accelerant) 27*/ 28#if defined(__cplusplus) 29extern "C" { 30#endif 31 32typedef struct { 33 sem_id sem; 34 int32 ben; 35} benaphore; 36 37#define INIT_BEN(x) x.sem = create_sem(0, "NV "#x" benaphore"); x.ben = 0; 38#define AQUIRE_BEN(x) if((atomic_add(&(x.ben), 1)) >= 1) acquire_sem(x.sem); 39#define RELEASE_BEN(x) if((atomic_add(&(x.ben), -1)) > 1) release_sem(x.sem); 40#define DELETE_BEN(x) delete_sem(x.sem); 41 42 43#define NV_PRIVATE_DATA_MAGIC 0x0009 /* a private driver rev, of sorts */ 44 45/* monitor setup */ 46#define CRTC1_TMDS 0x01 47#define CRTC2_TMDS 0x10 48#define CRTC1_VGA 0x02 49#define CRTC2_VGA 0x20 50 51/* dualhead extensions to flags */ 52#define DUALHEAD_OFF (0<<6) 53#define DUALHEAD_CLONE (1<<6) 54#define DUALHEAD_ON (2<<6) 55#define DUALHEAD_SWITCH (3<<6) 56#define DUALHEAD_BITS (3<<6) 57#define DUALHEAD_CAPABLE (1<<8) 58#define TV_BITS (3<<9) 59#define TV_MON (0<<9) 60#define TV_PAL (1<<9) 61#define TV_NTSC (2<<9) 62#define TV_CAPABLE (1<<11) 63#define TV_VIDEO (1<<12) 64#define TV_PRIMARY (1<<13) 65 66/* additional timing flags for GetMode/SetMode for Haiku ScreenPrefs panel */ 67enum { 68 RADEON_MODE_MULTIMON_REQUEST = 1 << 25, 69 RADEON_MODE_MULTIMON_REPLY = 1 << 26 70}; 71 72/* operation codes tunneled via ProposeDisplayMode for Haiku ScreenPrefs panel */ 73typedef enum { 74 ms_swap = 'sw', 75 ms_use_laptop_panel = 'up', 76 ms_tv_standard = 'tv' 77} multi_mon_settings; 78 79 80#define SKD_MOVE_CURSOR 0x00000001 81#define SKD_PROGRAM_CLUT 0x00000002 82#define SKD_SET_START_ADDR 0x00000004 83#define SKD_SET_CURSOR 0x00000008 84#define SKD_HANDLER_INSTALLED 0x80000000 85 86enum { 87 NV_GET_PRIVATE_DATA = B_DEVICE_OP_CODES_END + 1, 88 NV_GET_PCI, 89 NV_SET_PCI, 90 NV_DEVICE_NAME, 91 NV_RUN_INTERRUPTS, 92 NV_GET_NTH_AGP_INFO, 93 NV_ENABLE_AGP, 94 NV_ISA_OUT, 95 NV_ISA_IN 96}; 97 98/* card_type in order of date of NV chip design */ 99enum { 100 NV04 = 0, 101 NV05, 102 NV05M64, 103 NV06, 104 NV10, 105 NV11, 106 NV15, 107 NV17, 108 NV18, 109 NV20, 110 NV25, 111 NV28, 112 NV30, 113 NV31, 114 NV34, 115 NV35, 116 NV36, 117 NV38, 118 NV40, 119 NV41, 120 NV43, 121 NV44, 122 NV45, 123 G70, 124 G71, 125 G72, 126 G73, 127 G86, 128 G92 129}; 130 131/* card_arch in order of date of NV chip design */ 132enum { 133 NV04A = 0, 134 NV10A, 135 NV20A, 136 NV30A, 137 NV40A, 138 NV50A 139}; 140 141/* card info - information gathered from PINS (and other sources) */ 142enum 143{ // tv_encoder_type in order of capability (more or less) 144 NONE = 0, 145 CH7003, 146 CH7004, 147 CH7005, 148 CH7006, 149 CH7007, 150 CH7008, 151 SAA7102, 152 SAA7103, 153 SAA7104, 154 SAA7105, 155 BT868, 156 BT869, 157 CX25870, 158 CX25871, 159 NVIDIA 160}; 161 162/* handles to pre-defined engine commands */ 163#define NV_ROP5_SOLID 0x00000000 /* 2D */ 164#define NV_IMAGE_BLACK_RECTANGLE 0x00000001 /* 2D/3D */ 165#define NV_IMAGE_PATTERN 0x00000002 /* 2D */ 166#define NV_SCALED_IMAGE_FROM_MEMORY 0x00000003 /* 2D */ 167#define NV_TCL_PRIMITIVE_3D 0x00000004 /* 3D */ //2007 168#define NV4_SURFACE 0x00000010 /* 2D */ 169#define NV10_CONTEXT_SURFACES_2D 0x00000010 /* 2D */ 170#define NV_IMAGE_BLIT 0x00000011 /* 2D */ 171#define NV12_IMAGE_BLIT 0x00000011 /* 2D */ 172/* fixme: 173 * never use NV3_GDI_RECTANGLE_TEXT for DMA acceleration: 174 * There's a hardware fault in the input->output colorspace conversion here. 175 * Besides, in NV40 and up this command nolonger exists. Both 'facts' are confirmed 176 * by testing. 177 */ 178//#define NV3_GDI_RECTANGLE_TEXT 0x00000012 /* 2D */ 179#define NV4_GDI_RECTANGLE_TEXT 0x00000012 /* 2D */ 180#define NV4_CONTEXT_SURFACES_ARGB_ZS 0x00000013 /* 3D */ 181#define NV10_CONTEXT_SURFACES_ARGB_ZS 0x00000013 /* 3D */ 182#define NV4_DX5_TEXTURE_TRIANGLE 0x00000014 /* 3D */ 183#define NV10_DX5_TEXTURE_TRIANGLE 0x00000014 /* 3D */ 184#define NV4_DX6_MULTI_TEXTURE_TRIANGLE 0x00000015 /* unused (yet?) */ 185#define NV10_DX6_MULTI_TEXTURE_TRIANGLE 0x00000015 /* unused (yet?) */ 186#define NV1_RENDER_SOLID_LIN 0x00000016 /* 2D: unused */ 187 188/* max. number of overlay buffers */ 189#define MAXBUFFERS 3 190 191//----------------------------------------------------------------------------------- 192/* safety byte-offset from end of cardRAM for preventing acceleration engine crashes 193 * caused by the existance of DMA engine command buffers in cardRAM and/or fifo 194 * channel engine command re-assigning on-the-fly */ 195 196/* pre-NV40 notes: 197 * - we need at least 70kB distance from the end of RAM for fifo-reassigning 'bug' 198 * (confirmed on a TNT1); 199 * - keep extra failsafe room to prevent malfunctioning apps from crashing engine. */ 200#define PRE_NV40_OFFSET 80 * 1024 201 202/* NV40 and higher notes: 203 * - we need at least 416kB distance from the DMA command buffer: 204 * If you get too close to the DMA command buffer on NV40 and NV43 at least (both 205 * confirmed), the source DMA instance will mess-up for at least engine command 206 * NV_IMAGE_BLIT and NV12_IMAGE_BLIT; 207 * - we need at least ???kB distance from the end of RAM for fifo-reassigning 'bug' 208 * (fixme: unknown yet because fifo assignment switching isn't used here atm); 209 * - keep extra failsafe room to prevent malfunctioning apps from crashing engine. */ 210#define NV40_PLUS_OFFSET 512 * 1024 211 212/* fifo re-assigning bug definition: 213 * if the fifo assignment is changed while at the same time card memory in the 214 * dangerous region is being accessed by some application, the engine will crash. 215 * This bug applies for both PIO and DMA mode acceleration! */ 216 217/* source-DMA instance bug definition: 218 * if card memory in the dangerous region is being accessed by some application while 219 * a DMA command buffer exists in the same memory (though in a different place), 220 * the engine will crash. */ 221//----------------------------------------------------------------------------------- 222 223/* internal used info on overlay buffers */ 224typedef struct { 225 uint16 slopspace; 226 uint32 size; 227} int_buf_info; 228 229typedef struct { // apsed, see comments in nvidia.settings 230 // for driver 231 char accelerant[B_FILE_NAME_LENGTH]; 232 char primary[B_FILE_NAME_LENGTH]; 233 bool dumprom; 234 // for accelerant 235 uint32 logmask; 236 uint32 memory; 237 uint32 tv_output; 238 bool usebios; 239 bool hardcursor; 240 bool switchhead; 241 bool force_pci; 242 bool unhide_fw; 243 bool pgm_panel; 244 bool dma_acc; 245 bool vga_on_tv; 246 bool force_sync; 247 bool force_ws; 248 bool block_acc; 249 uint32 gpu_clk; 250 uint32 ram_clk; 251 bool check_edid; 252} nv_settings; 253 254/* monitor info gathered via EDID */ 255typedef struct { 256 bool have_native_edid; /* gathered 'native' EDID either via DDC or via GPU */ 257 bool digital; /* screen connection type: analog (VGA) or digital (DVI) */ 258 display_timing timing; /* 'native modeline' fetched for screen */ 259 float aspect; /* screen's aspect ratio */ 260 bool have_full_edid; /* EDID read succesfully via DDC */ 261 edid1_info full_edid; /* complete EDID info as fetched via DDC */ 262} edid_specs; 263 264/* shared info */ 265typedef struct { 266 /* a few ID things */ 267 uint16 vendor_id; /* PCI vendor ID, from pci_info */ 268 uint16 device_id; /* PCI device ID, from pci_info */ 269 uint8 revision; /* PCI device revsion, from pci_info */ 270 uint8 bus; /* PCI bus number, from pci_info */ 271 uint8 device; /* PCI device number on bus, from pci_info */ 272 uint8 function; /* PCI function number in device, from pci_info */ 273 274 /* used to return status for INIT_ACCELERANT and CLONE_ACCELERANT */ 275 bool accelerant_in_use; 276 277 /* bug workaround for 4.5.0 */ 278 uint32 use_clone_bugfix; /*for 4.5.0, cloning of physical memory does not work*/ 279 uint32 * clone_bugfix_regs; 280 281 /*memory mappings*/ 282 area_id regs_area; /* Kernel's area_id for the memory mapped registers. 283 It will be cloned into the accelerant's address 284 space. */ 285 286 area_id fb_area; /* Frame buffer's area_id. The addresses are shared with all teams. */ 287 area_id unaligned_dma_area; /* Area assigned for DMA. It will be (partially) mapped to an 288 aligned area using MTRR-WC. */ 289 area_id dma_area; /* Aligned area assigned for DMA. The addresses are shared with all teams. */ 290 291 void *framebuffer; /* As viewed from virtual memory */ 292 void *framebuffer_pci; /* As viewed from the PCI bus (for DMA) */ 293 void *dma_buffer; /* As viewed from virtual memory */ 294 void *dma_buffer_pci; /* As viewed from the PCI bus (for DMA) */ 295 296 /*screenmode list*/ 297 area_id mode_area; /* Contains the list of display modes the driver supports */ 298 uint32 mode_count; /* Number of display modes in the list */ 299 300 /*flags - used by driver*/ 301 uint32 flags; 302 303 /*vblank semaphore*/ 304 sem_id vblank; /* The vertical blank semaphore. Ownership will be 305 transfered to the team opening the device first */ 306 /*cursor information*/ 307 struct { 308 uint16 hot_x; /* Cursor hot spot. The top left corner of the cursor */ 309 uint16 hot_y; /* is 0,0 */ 310 uint16 x; /* The location of the cursor hot spot on the */ 311 uint16 y; /* desktop */ 312 uint16 width; /* Width and height of the cursor shape (always 16!) */ 313 uint16 height; 314 bool is_visible; /* Is the cursor currently displayed? */ 315 bool dh_right; /* Is cursor on right side of stretched screen? */ 316 } cursor; 317 318 /*colour lookup table*/ 319 uint8 color_data[3 * 256]; /* Colour lookup table - as used by DAC */ 320 321 /*more display mode stuff*/ 322 display_mode dm; /* current display mode configuration: head1 */ 323 uint32 dpms_flags; /* current DPMS mode */ 324 bool acc_mode; /* signals (non)accelerated mode */ 325 bool interlaced_tv_mode;/* signals interlaced CRTC TV output mode */ 326 bool crtc_switch_mode; /* signals dualhead switch mode if panels are used */ 327 bool haiku_prefs_used; /* signals use of Haiku ScreenPrefs app for special modes */ 328 bool Haiku_switch_head; /* signals Haiku ScreenPrefs panel want inverted mode later on */ 329 330 /*frame buffer config - for BDirectScreen*/ 331 frame_buffer_config fbc; /* bytes_per_row and start of frame buffer: head1 */ 332 accelerant_device_info adi; /* as returned by hook GET_ACCELERANT_DEVICE_INFO */ 333 334 /*acceleration engine*/ 335 struct { 336 uint32 count; /* last dwgsync slot used */ 337 uint32 last_idle; /* last dwgsync slot we *know* the engine was idle after */ 338 benaphore lock; /* for serializing access to the acc engine */ 339 struct { 340 uint32 handle[0x08]; /* FIFO channel's cmd handle for the owning cmd */ 341 uint32 ch_ptr[0x20]; /* cmd handle's ptr to it's assigned FIFO ch (if any) */ 342 } fifo; 343 struct { 344 uint32 put; /* last 32-bit-word adress given to engine to exec. to */ 345 uint32 current; /* first free 32-bit-word adress in buffer */ 346 uint32 free; /* nr. of useable free 32-bit words remaining in buffer */ 347 uint32 max; /* command buffer's useable size in 32-bit words */ 348 } dma; 349 bool agp_mode; /* card is running in AGP mode */ 350 struct { 351 uint32 clones; /* clone 'number' (mask, slot) (one bit per clone) */ 352 uint32 reload; /* reload state and surfaces (one bit per clone) */ 353 uint32 newmode; /* re-allocate all buffers (one bit per clone) */ 354 //fixme: memory stuff needs to be expanded (shared texture allocation?) 355 uint32 mem_low; /* ptr to first free mem adress: cardmem local offset */ 356 uint32 mem_high; /* ptr to last free mem adress: cardmem local offset */ 357 bool mode_changing; /* a mode-change is in progress (set/clear by 2D drv) */ 358 } threeD; 359 } engine; 360 361 struct 362 { 363 /* specialised registers for card initialisation read from NV BIOS (pins) */ 364 365 /* general card information */ 366 uint32 card_type; /* see card_type enum above */ 367 uint32 card_arch; /* see card_arch enum above */ 368 bool laptop; /* mobile chipset or not ('internal' flatpanel!) */ 369 bool slaved_tmds1; /* external TMDS encoder active on CRTC1 */ 370 bool slaved_tmds2; /* external TMDS encoder active on CRTC2 */ 371 bool master_tmds1; /* on die TMDS encoder active on CRTC1 */ 372 bool master_tmds2; /* on die TMDS encoder active on CRTC2 */ 373 display_timing p1_timing; /* 'modeline' fetched for panel at CRTC1 */ 374 display_timing p2_timing; /* 'modeline' fetched for panel at CRTC2 */ 375 edid_specs con1_screen; /* EDID properties of the screen connected to connector 1 */ 376 edid_specs con2_screen; /* EDID properties of the screen connected to connector 2 */ 377 edid_specs crtc1_screen; /* EDID properties of the screen connected to CRTC1 */ 378 edid_specs crtc2_screen; /* EDID properties of the screen connected to CRTC2 */ 379 bool crtc2_prim; /* using CRTC2 as primary CRTC */ 380 bool i2c_bus0; /* we have a wired I2C bus 0 on board */ 381 bool i2c_bus1; /* we have a wired I2C bus 1 on board */ 382 bool i2c_bus2; /* we have a wired I2C bus 2 on board */ 383 struct 384 { 385 uint32 type; /* see tvchip_type enum above */ 386 uint8 version; /* chip silicon version */ 387 uint8 bus; /* I2C bus on which TVout chip resides */ 388 uint8 adress; /* I2C adress on which TVout chip resides */ 389 } tv_encoder; 390 uint8 monitors; /* output devices connection matrix */ 391 bool int_assigned; /* card has a useable INT assigned to it */ 392 status_t pins_status; /* B_OK if read correctly, B_ERROR if faked */ 393 394 /* PINS */ 395 float f_ref; /* PLL reference-oscillator frequency (Mhz) */ 396 bool ext_pll; /* the extended PLL contains more dividers */ 397 uint32 max_system_vco; /* graphics engine PLL VCO limits (Mhz) */ 398 uint32 min_system_vco; 399 uint32 max_pixel_vco; /* dac1 PLL VCO limits (Mhz) */ 400 uint32 min_pixel_vco; 401 uint32 max_video_vco; /* dac2 PLL VCO limits (Mhz) */ 402 uint32 min_video_vco; 403 uint32 std_engine_clock; /* graphics engine clock speed needed (Mhz) */ 404 uint32 std_memory_clock; /* card memory clock speed needed (Mhz) */ 405 uint32 max_dac1_clock; /* dac1 limits (Mhz) */ 406 uint32 max_dac1_clock_8; /* dac1 limits correlated to RAMspeed limits (Mhz) */ 407 uint32 max_dac1_clock_16; 408 uint32 max_dac1_clock_24; 409 uint32 max_dac1_clock_32; 410 uint32 max_dac1_clock_32dh; 411 uint32 max_dac2_clock; /* dac2 limits (Mhz) */ 412 uint32 max_dac2_clock_8; /* dac2, maven limits correlated to RAMspeed limits (Mhz) */ 413 uint32 max_dac2_clock_16; 414 uint32 max_dac2_clock_24; 415 uint32 max_dac2_clock_32; 416 uint32 max_dac2_clock_32dh; 417 bool secondary_head; /* presence of functions */ 418 bool tvout; 419 bool primary_dvi; 420 bool secondary_dvi; 421 uint32 memory_size; /* memory (in bytes) */ 422 } ps; 423 424 /* mirror of the ROM (copied in driver, because may not be mapped permanently) */ 425 uint8 rom_mirror[65536]; 426 427 /* some configuration settings from ~/config/settings/kernel/drivers/nv.settings if exists */ 428 nv_settings settings; 429 430 struct 431 { 432 overlay_buffer myBuffer[MAXBUFFERS];/* scaler input buffers */ 433 int_buf_info myBufInfo[MAXBUFFERS]; /* extra info on scaler input buffers */ 434 overlay_token myToken; /* scaler is free/in use */ 435 benaphore lock; /* for creating buffers and aquiring overlay unit routines */ 436 bool crtc; /* location of overlay unit */ 437 /* variables needed for virtualscreens (move_overlay()): */ 438 bool active; /* true is overlay currently in use */ 439 overlay_window ow; /* current position of overlay output window */ 440 overlay_buffer ob; /* current inputbuffer in use */ 441 overlay_view my_ov; /* current corrected view in inputbuffer */ 442 uint32 h_ifactor; /* current 'unclipped' horizontal inverse scaling factor */ 443 uint32 v_ifactor; /* current 'unclipped' vertical inverse scaling factor */ 444 } overlay; 445 446} shared_info; 447 448/* Read or write a value in PCI configuration space */ 449typedef struct { 450 uint32 magic; /* magic number to make sure the caller groks us */ 451 uint32 offset; /* Offset to read/write */ 452 uint32 size; /* Number of bytes to transfer */ 453 uint32 value; /* The value read or written */ 454} nv_get_set_pci; 455 456/* Enable or Disable CRTC (1,2) interrupts */ 457typedef struct { 458 uint32 magic; /* magic number to make sure the caller groks us */ 459 bool crtc; /* adressed CRTC */ 460 bool do_it; /* state to set */ 461} nv_set_vblank_int; 462 463/* Retrieve the area_id of the kernel/accelerant shared info */ 464typedef struct { 465 uint32 magic; /* magic number to make sure the caller groks us */ 466 area_id shared_info_area; /* area_id containing the shared information */ 467} nv_get_private_data; 468 469/* Retrieve the device name. Usefull for when we have a file handle, but want 470to know the device name (like when we are cloning the accelerant) */ 471typedef struct { 472 uint32 magic; /* magic number to make sure the caller groks us */ 473 char *name; /* The name of the device, less the /dev root */ 474} nv_device_name; 475 476/* Retrieve an AGP device interface if there. Usefull to find the AGP speed scheme 477used (pre 3.x or 3.x) */ 478typedef struct { 479 uint32 magic; /* magic number to make sure the caller groks us */ 480 bool agp_bus;/* indicates if we have access to the AGP busmanager */ 481 uint8 index; /* device index in list of devices found */ 482 bool exist; /* we got AGP device info */ 483 agp_info agpi; /* AGP interface info of a device */ 484} nv_nth_agp_info; 485 486/* Execute an AGP command */ 487typedef struct { 488 uint32 magic; /* magic number to make sure the caller groks us */ 489 bool agp_bus;/* indicates if we have access to the AGP busmanager */ 490 uint32 cmd; /* actual command to execute */ 491} nv_cmd_agp; 492 493/* Read or write a value in ISA I/O space */ 494typedef struct { 495 uint32 magic; /* magic number to make sure the caller groks us */ 496 uint16 adress; /* Offset to read/write */ 497 uint8 size; /* Number of bytes to transfer */ 498 uint16 data; /* The value read or written */ 499} nv_in_out_isa; 500 501enum { 502 503 _WAIT_FOR_VBLANK = (1 << 0) 504}; 505 506#if defined(__cplusplus) 507} 508#endif 509 510 511#endif 512