1/* Read initialisation information from card */ 2/* some bits are hacks, where PINS is not known */ 3/* Author: 4 Rudolf Cornelissen 7/2003-4/2021 5*/ 6 7#define MODULE_BIT 0x00002000 8 9#include "nv_std.h" 10 11/* pins V5.16 and up ROM infoblock stuff */ 12typedef struct { 13 uint16 InitScriptTablePtr; /* ptr to list of ptrs to scripts to exec */ 14 uint16 MacroIndexTablePtr; /* ptr to list with indexes and sizes of items in MacroTable */ 15 uint16 MacroTablePtr; /* ptr to list with items containing multiple 32bit reg writes */ 16 uint16 ConditionTablePtr; /* ptr to list of PCI regs and bits to tst for exec mode */ 17 uint16 IOConditionTablePtr; /* ptr to list of ISA regs and bits to tst for exec mode */ 18 uint16 IOFlagConditionTablePtr;/* ptr to list of ISA regs and bits to tst, ref'd to a matrix, for exec mode */ 19 uint16 InitFunctionTablePtr; /* ptr to list of startadresses of fixed ROM init routines */ 20} PinsTables; 21 22static void detect_panels(void); 23static void setup_output_matrix(void); 24static void pinsnv4_fake(void); 25static void pinsnv5_nv5m64_fake(void); 26static void pinsnv6_fake(void); 27static void pinsnv10_arch_fake(void); 28static void pinsnv20_arch_fake(void); 29static void pinsnv30_arch_fake(void); 30static void getRAMsize_arch_nv4(void); 31static void getstrap_arch_nv4(void); 32static void getRAMsize_arch_nv10_20_30_40(void); 33static void getstrap_arch_nv10_20_30_40(void); 34static status_t pins2_read(uint8 *rom, uint32 offset); 35static status_t pins3_5_read(uint8 *rom, uint32 offset); 36static status_t coldstart_card(uint8* rom, uint16 init1, uint16 init2, uint16 init_size, uint16 ram_tab); 37static status_t coldstart_card_516_up(uint8* rom, PinsTables tabs, uint16 ram_tab); 38static status_t exec_type1_script(uint8* rom, uint16 adress, int16* size, uint16 ram_tab); 39static status_t exec_type2_script(uint8* rom, uint16 adress, int16* size, PinsTables tabs, uint16 ram_tab); 40static status_t exec_type2_script_mode(uint8* rom, uint16* adress, int16* size, PinsTables tabs, uint16 ram_tab, bool* exec); 41static void exec_cmd_39_type2(uint8* rom, uint32 data, PinsTables tabs, bool* exec); 42static void log_pll(uint32 reg, uint32 freq); 43static void setup_ram_config(uint8* rom, uint16 ram_tab); 44static void setup_ram_config_nv10_up(uint8* rom); 45static void setup_ram_config_nv28(uint8* rom); 46static status_t translate_ISA_PCI(uint32* reg); 47static status_t nv_crtc_setup_fifo(void); 48 49/* Parse the BIOS PINS structure if there */ 50status_t parse_pins () 51{ 52 uint8 *rom; 53 uint8 chksum = 0; 54 int i; 55 uint32 offset; 56 status_t result = B_ERROR; 57 58 /* preset PINS read status to failed */ 59 si->ps.pins_status = B_ERROR; 60 61 /* check the validity of PINS */ 62 LOG(2,("INFO: Reading PINS info\n")); 63 rom = (uint8 *) si->rom_mirror; 64 /* check BIOS signature - this is defined in the PCI standard */ 65 if (rom[0]!=0x55 || rom[1]!=0xaa) 66 { 67 LOG(8,("INFO: BIOS signature not found\n")); 68 return B_ERROR; 69 } 70 LOG(2,("INFO: BIOS signature $AA55 found OK\n")); 71 72 /* find the PINS struct adress */ 73 for (offset = 0; offset < 65536; offset++) 74 { 75 if (rom[offset ] != 0xff) continue; 76 if (rom[offset + 1] != 0x7f) continue; 77 if (rom[offset + 2] != 0x4e) continue; /* N */ 78 if (rom[offset + 3] != 0x56) continue; /* V */ 79 if (rom[offset + 4] != 0x00) continue; 80 81 LOG(8,("INFO: PINS signature found\n")); 82 break; 83 } 84 85 if (offset > 65535) 86 { 87 LOG(8,("INFO: PINS signature not found\n")); 88 return B_ERROR; 89 } 90 91 /* verify PINS checksum */ 92 for (i = 0; i < 8; i++) 93 { 94 chksum += rom[offset + i]; 95 } 96 if (chksum) 97 { 98 LOG(8,("INFO: PINS checksum error\n")); 99 return B_ERROR; 100 } 101 102 /* checkout PINS struct version */ 103 LOG(2,("INFO: PINS checksum is OK; PINS version is %d.%d\n", 104 rom[offset + 5], rom[offset + 6])); 105 106 /* update the si->ps struct as far as is possible and coldstart card */ 107 //fixme: NV40 and up(?) nolonger use this system... 108 switch (rom[offset + 5]) 109 { 110 case 2: 111 result = pins2_read(rom, offset); 112 break; 113 case 3: 114 case 4: 115 case 5: 116 result = pins3_5_read(rom, offset); 117 break; 118 default: 119 LOG(8,("INFO: unknown PINS version\n")); 120 return B_ERROR; 121 break; 122 } 123 124 /* check PINS read result */ 125 if (result == B_ERROR) 126 { 127 LOG(8,("INFO: PINS read/decode/execute error\n")); 128 return B_ERROR; 129 } 130 /* PINS scan succeeded */ 131 si->ps.pins_status = B_OK; 132 LOG(2,("INFO: PINS scan completed succesfully\n")); 133 return B_OK; 134} 135 136 137static status_t pins2_read(uint8 *rom, uint32 offset) 138{ 139 uint16 init1 = rom[offset + 18] + (rom[offset + 19] * 256); 140 uint16 init2 = rom[offset + 20] + (rom[offset + 21] * 256); 141 uint16 init_size = rom[offset + 22] + (rom[offset + 23] * 256) + 1; 142 /* confirmed by comparing cards */ 143 uint16 ram_tab = init1 - 0x0010; 144 /* fixme: PPC BIOSes (might) return NULL pointers for messages here */ 145 unsigned char* signon_msg 146 = &(rom[(rom[offset + 24] + (rom[offset + 25] * 256))]); 147 unsigned char* vendor_name 148 = &(rom[(rom[offset + 40] + (rom[offset + 41] * 256))]); 149 unsigned char* product_name 150 = &(rom[(rom[offset + 42] + (rom[offset + 43] * 256))]); 151 unsigned char* product_rev 152 = &(rom[(rom[offset + 44] + (rom[offset + 45] * 256))]); 153 154 LOG(8, ("INFO: cmdlist 1: $%04x, 2: $%04x, max. size $%04x\n", init1, init2, 155 init_size)); 156 LOG(8, ("INFO: signon msg:\n%s\n", signon_msg)); 157 LOG(8, ("INFO: vendor name: %s\n", vendor_name)); 158 LOG(8, ("INFO: product name: %s\n", product_name)); 159 LOG(8, ("INFO: product rev: %s\n", product_rev)); 160 161 return coldstart_card(rom, init1, init2, init_size, ram_tab); 162} 163 164 165static status_t pins3_5_read(uint8 *rom, uint32 offset) 166{ 167 uint16 init1 = rom[offset + 18] + (rom[offset + 19] * 256); 168 uint16 init2 = rom[offset + 20] + (rom[offset + 21] * 256); 169 uint16 init_size = rom[offset + 22] + (rom[offset + 23] * 256) + 1; 170 /* confirmed on a TNT2-M64 with pins V5.1 */ 171 uint16 ram_tab = rom[offset + 24] + (rom[offset + 25] * 256); 172 /* fixme: PPC BIOSes (might) return NULL pointers for messages here */ 173 unsigned char* signon_msg 174 = &(rom[(rom[offset + 30] + (rom[offset + 31] * 256))]); 175 unsigned char* vendor_name 176 = &(rom[(rom[offset + 46] + (rom[offset + 47] * 256))]); 177 unsigned char* product_name 178 = &(rom[(rom[offset + 48] + (rom[offset + 49] * 256))]); 179 unsigned char* product_rev 180 = &(rom[(rom[offset + 50] + (rom[offset + 51] * 256))]); 181 182 LOG(8, ("INFO: pre PINS 5.16 cmdlist 1: $%04x, 2: $%04x, max. size $%04x\n", 183 init1, init2, init_size)); 184 LOG(8, ("INFO: signon msg:\n%s\n", signon_msg)); 185 LOG(8, ("INFO: vendor name: %s\n", vendor_name)); 186 LOG(8, ("INFO: product name: %s\n", product_name)); 187 LOG(8, ("INFO: product rev: %s\n", product_rev)); 188 189 /* pins 5.06 and higher has VCO range info */ 190 if (((rom[offset + 5]) == 5) && ((rom[offset + 6]) >= 0x06)) 191 { 192 /* get PLL VCO range info */ 193 uint32 fvco_max = *((uint32*)(&(rom[offset + 67]))); 194 uint32 fvco_min = *((uint32*)(&(rom[offset + 71]))); 195 196 LOG(8,("INFO: PLL VCO range is %dkHz - %dkHz\n", fvco_min, fvco_max)); 197 198 /* modify presets to reflect card capability */ 199 si->ps.min_system_vco = fvco_min / 1000; 200 si->ps.max_system_vco = fvco_max / 1000; 201 //fixme: enable and modify PLL code... 202 //si->ps.min_pixel_vco = fvco_min / 1000; 203 //si->ps.max_pixel_vco = fvco_max / 1000; 204 //si->ps.min_video_vco = fvco_min / 1000; 205 //si->ps.max_video_vco = fvco_max / 1000; 206 } 207 208 //fixme: add 'parsing scripts while not actually executing' as warmstart method, 209 // instead of not parsing at all: this will update the driver's speeds 210 // as below, while logging the scripts as well (for our learning pleasure :) 211 212 /* pins 5.16 and higher is more extensive, and works differently from before */ 213 if (((rom[offset + 5]) == 5) && ((rom[offset + 6]) >= 0x10)) 214 { 215 /* pins 5.16 and up have a more extensive command list table, and have more 216 * commands to choose from as well. */ 217 PinsTables tabs; 218 tabs.InitScriptTablePtr = rom[offset + 75] + (rom[offset + 76] * 256); 219 tabs.MacroIndexTablePtr = rom[offset + 77] + (rom[offset + 78] * 256); 220 tabs.MacroTablePtr = rom[offset + 79] + (rom[offset + 80] * 256); 221 tabs.ConditionTablePtr = rom[offset + 81] + (rom[offset + 82] * 256); 222 tabs.IOConditionTablePtr = rom[offset + 83] + (rom[offset + 84] * 256); 223 tabs.IOFlagConditionTablePtr = rom[offset + 85] + (rom[offset + 86] * 256); 224 tabs.InitFunctionTablePtr = rom[offset + 87] + (rom[offset + 88] * 256); 225 226 LOG(8,("INFO: PINS 5.16 and later cmdlist pointers:\n")); 227 LOG(8,("INFO: InitScriptTablePtr: $%04x\n", tabs.InitScriptTablePtr)); 228 LOG(8,("INFO: MacroIndexTablePtr: $%04x\n", tabs.MacroIndexTablePtr)); 229 LOG(8,("INFO: MacroTablePtr: $%04x\n", tabs.MacroTablePtr)); 230 LOG(8,("INFO: ConditionTablePtr: $%04x\n", tabs.ConditionTablePtr)); 231 LOG(8,("INFO: IOConditionTablePtr: $%04x\n", tabs.IOConditionTablePtr)); 232 LOG(8,("INFO: IOFlagConditionTablePtr: $%04x\n", tabs.IOFlagConditionTablePtr)); 233 LOG(8,("INFO: InitFunctionTablePtr: $%04x\n", tabs.InitFunctionTablePtr)); 234 235 return coldstart_card_516_up(rom, tabs, ram_tab); 236 } 237 else 238 { 239 /* pre 'pins 5.16' still uses the 'old' method in which the command list 240 * table always has two entries. */ 241 return coldstart_card(rom, init1, init2, init_size, ram_tab); 242 } 243} 244 245static status_t coldstart_card(uint8* rom, uint16 init1, uint16 init2, uint16 init_size, uint16 ram_tab) 246{ 247 status_t result = B_OK; 248 int16 size = init_size; 249 250 LOG(8,("INFO: now executing coldstart...\n")); 251 252 /* select colormode CRTC registers base adresses */ 253 NV_REG8(NV8_MISCW) = 0xcb; 254 255 /* unknown.. */ 256 NV_REG8(NV8_VSE2) = 0x01; 257 258 /* enable access to primary head */ 259 set_crtc_owner(0); 260 /* unlock head's registers for R/W access */ 261 CRTCW(LOCK, 0x57); 262 CRTCW(VSYNCE ,(CRTCR(VSYNCE) & 0x7f)); 263 /* disable RMA as it's not used */ 264 /* (RMA is the cmd register for the 32bit port in the GPU to access 32bit registers 265 * and framebuffer via legacy ISA I/O space.) */ 266 CRTCW(RMA, 0x00); 267 268 if (si->ps.secondary_head) 269 { 270 /* enable access to secondary head */ 271 set_crtc_owner(1); 272 /* unlock head's registers for R/W access */ 273 CRTC2W(LOCK, 0x57); 274 CRTC2W(VSYNCE ,(CRTCR(VSYNCE) & 0x7f)); 275 } 276 277 /* turn off both displays and the hardcursors (also disables transfers) */ 278 nv_crtc_dpms(false, false, false, true); 279 nv_crtc_cursor_hide(); 280 if (si->ps.secondary_head) 281 { 282 nv_crtc2_dpms(false, false, false, true); 283 nv_crtc2_cursor_hide(); 284 } 285 286 /* execute BIOS coldstart script(s) */ 287 if (init1 || init2) 288 { 289 if (init1) 290 if (exec_type1_script(rom, init1, &size, ram_tab) != B_OK) result = B_ERROR; 291 if (init2 && (result == B_OK)) 292 if (exec_type1_script(rom, init2, &size, ram_tab) != B_OK) result = B_ERROR; 293 294 /* now enable ROM shadow or the card will remain shut-off! */ 295 CFGW(ROMSHADOW, (CFGR(ROMSHADOW) |= 0x00000001)); 296 297 //temporary: should be called from setmode probably.. 298 nv_crtc_setup_fifo(); 299 } 300 else 301 { 302 result = B_ERROR; 303 } 304 305 if (result != B_OK) 306 LOG(8,("INFO: coldstart failed.\n")); 307 else 308 LOG(8,("INFO: coldstart execution completed OK.\n")); 309 310 return result; 311} 312 313static status_t coldstart_card_516_up(uint8* rom, PinsTables tabs, uint16 ram_tab) 314{ 315 status_t result = B_OK; 316 uint16 adress; 317 uint32 fb_mrs1 = 0; 318 uint32 fb_mrs2 = 0; 319 320 LOG(8,("INFO: now executing coldstart...\n")); 321 322 /* get some strapinfo(?) for NV28 framebuffer access */ 323 //fixme?: works on at least one NV28... how about other cards? 324 if (si->ps.card_type == NV28) 325 { 326 fb_mrs2 = NV_REG32(NV32_FB_MRS2); 327 fb_mrs1 = NV_REG32(NV32_FB_MRS1); 328 } 329 330 /* select colormode CRTC registers base adresses */ 331 NV_REG8(NV8_MISCW) = 0xcb; 332 333 /* unknown.. */ 334 NV_REG8(NV8_VSE2) = 0x01; 335 336 /* enable access to primary head */ 337 set_crtc_owner(0); 338 /* unlock head's registers for R/W access */ 339 CRTCW(LOCK, 0x57); 340 CRTCW(VSYNCE ,(CRTCR(VSYNCE) & 0x7f)); 341 /* disable RMA as it's not used */ 342 /* (RMA is the cmd register for the 32bit port in the GPU to access 32bit registers 343 * and framebuffer via legacy ISA I/O space.) */ 344 CRTCW(RMA, 0x00); 345 346 if (si->ps.secondary_head) 347 { 348 /* enable access to secondary head */ 349 set_crtc_owner(1); 350 /* unlock head's registers for R/W access */ 351 CRTC2W(LOCK, 0x57); 352 CRTC2W(VSYNCE ,(CRTCR(VSYNCE) & 0x7f)); 353 } 354 355 /* turn off both displays and the hardcursors (also disables transfers) */ 356 nv_crtc_dpms(false, false, false, true); 357 nv_crtc_cursor_hide(); 358 if (si->ps.secondary_head) 359 { 360 nv_crtc2_dpms(false, false, false, true); 361 nv_crtc2_cursor_hide(); 362 } 363 364 /* execute all BIOS coldstart script(s) */ 365 if (tabs.InitScriptTablePtr) 366 { 367 /* size is nolonger used, keeping it anyway for testing purposes :) */ 368 int16 size = 32767; 369 uint16 index = tabs.InitScriptTablePtr; 370 371 adress = *((uint16*)(&(rom[index]))); 372 if (!adress) 373 { 374 LOG(8,("INFO: no cmdlist found!\n")); 375 result = B_ERROR; 376 } 377 378 while (adress && (result == B_OK)) 379 { 380 result = exec_type2_script(rom, adress, &size, tabs, ram_tab); 381 /* next command script, please */ 382 index += 2; 383 adress = *((uint16*)(&(rom[index]))); 384 } 385 386 /* do some NV28 specific extra stuff */ 387 //fixme: NV28 only?? 388 if (si->ps.card_type == NV28) 389 { 390 /* setup PTIMER */ 391 ACCW(PT_NUMERATOR, (si->ps.std_engine_clock * 20)); 392 ACCW(PT_DENOMINATR, 0x00000271); 393 394 /* get NV28 RAM access up and running */ 395 //fixme?: works on at least one NV28... how about other cards? 396 NV_REG32(NV32_FB_MRS2) = fb_mrs2; 397 NV_REG32(NV32_FB_MRS1) = fb_mrs1; 398 } 399 400 /* now enable ROM shadow or the card will remain shut-off! */ 401 CFGW(ROMSHADOW, (CFGR(ROMSHADOW) |= 0x00000001)); 402 403 //temporary: should be called from setmode probably.. 404 nv_crtc_setup_fifo(); 405 } 406 else 407 { 408 result = B_ERROR; 409 } 410 411 if (result != B_OK) 412 LOG(8,("INFO: coldstart failed.\n")); 413 else 414 LOG(8,("INFO: coldstart execution completed OK.\n")); 415 416 return result; 417} 418 419/* This routine is complete, and is used for pre-NV10 cards. It's tested on a Elsa 420 * Erazor III with TNT2 (NV05) and on two no-name TNT2-M64's. All cards coldstart 421 * perfectly. */ 422static status_t exec_type1_script(uint8* rom, uint16 adress, int16* size, uint16 ram_tab) 423{ 424 status_t result = B_OK; 425 bool end = false; 426 bool exec = true; 427 uint8 index, byte; 428 uint32 reg, data, data2, and_out, or_in; 429 430 LOG(8,("\nINFO: executing type1 script at adress $%04x...\n", adress)); 431 LOG(8,("INFO: ---Executing following command(s):\n")); 432 433 while (!end) 434 { 435 LOG(8,("INFO: $%04x ($%02x); ", adress, rom[adress])); 436 437 switch (rom[adress]) 438 { 439 case 0x59: 440 *size -= 7; 441 if (*size < 0) 442 { 443 LOG(8,("script size error, aborting!\n\n")); 444 end = true; 445 result = B_ERROR; 446 break; 447 } 448 449 /* execute */ 450 adress += 1; 451 reg = *((uint32*)(&(rom[adress]))); 452 adress += 4; 453 data = *((uint16*)(&(rom[adress]))); 454 adress += 2; 455 data2 = *((uint16*)(&(rom[data]))); 456 LOG(8,("cmd 'calculate indirect and set PLL 32bit reg $%08x for %.3fMHz'\n", 457 reg, ((float)data2))); 458 if (exec) 459 { 460 float calced_clk; 461 uint8 m, n, p; 462 nv_dac_sys_pll_find(((float)data2), &calced_clk, &m, &n, &p, 0); 463 NV_REG32(reg) = ((p << 16) | (n << 8) | m); 464 } 465 log_pll(reg, data2); 466 break; 467 case 0x5a: 468 *size -= 7; 469 if (*size < 0) 470 { 471 LOG(8,("script size error, aborting!\n\n")); 472 end = true; 473 result = B_ERROR; 474 break; 475 } 476 477 /* execute */ 478 adress += 1; 479 reg = *((uint32*)(&(rom[adress]))); 480 adress += 4; 481 data = *((uint16*)(&(rom[adress]))); 482 adress += 2; 483 data2 = *((uint32*)(&(rom[data]))); 484 LOG(8,("cmd 'WR indirect 32bit reg' $%08x = $%08x\n", reg, data2)); 485 if (exec) NV_REG32(reg) = data2; 486 break; 487 case 0x63: 488 *size -= 1; 489 if (*size < 0) 490 { 491 LOG(8,("script size error, aborting!\n\n")); 492 end = true; 493 result = B_ERROR; 494 break; 495 } 496 497 /* execute */ 498 adress += 1; 499 LOG(8,("cmd 'setup RAM config' (always done)\n")); 500 /* always done */ 501 setup_ram_config(rom, ram_tab); 502 break; 503 case 0x65: 504 *size -= 13; 505 if (*size < 0) 506 { 507 LOG(8,("script size error, aborting!\n\n")); 508 end = true; 509 result = B_ERROR; 510 break; 511 } 512 513 /* execute */ 514 adress += 1; 515 reg = *((uint32*)(&(rom[adress]))); 516 adress += 4; 517 data = *((uint32*)(&(rom[adress]))); 518 adress += 4; 519 data2 = *((uint32*)(&(rom[adress]))); 520 adress += 4; 521 LOG(8,("cmd 'WR 32bit reg $%08x = $%08x, then = $%08x' (always done)\n", 522 reg, data, data2)); 523 /* always done */ 524 NV_REG32(reg) = data; 525 NV_REG32(reg) = data2; 526 CFGW(ROMSHADOW, (CFGR(ROMSHADOW) & 0xfffffffe)); 527 break; 528 case 0x69: 529 *size -= 5; 530 if (*size < 0) 531 { 532 LOG(8,("script size error, aborting!\n\n")); 533 end = true; 534 result = B_ERROR; 535 break; 536 } 537 538 /* execute */ 539 adress += 1; 540 reg = *((uint16*)(&(rom[adress]))); 541 adress += 2; 542 and_out = *((uint8*)(&(rom[adress]))); 543 adress += 1; 544 or_in = *((uint8*)(&(rom[adress]))); 545 adress += 1; 546 LOG(8,("cmd 'RD 8bit ISA reg $%04x, AND-out = $%02x, OR-in = $%02x, WR-bk'\n", 547 reg, and_out, or_in)); 548 if (exec) 549 { 550 translate_ISA_PCI(®); 551 byte = NV_REG8(reg); 552 byte &= (uint8)and_out; 553 byte |= (uint8)or_in; 554 NV_REG8(reg) = byte; 555 } 556 break; 557 case 0x6d: 558 *size -= 3; 559 if (*size < 0) 560 { 561 LOG(8,("script size error, aborting!\n\n")); 562 end = true; 563 result = B_ERROR; 564 break; 565 } 566 567 /* execute */ 568 adress += 1; 569 data = NV_REG32(NV32_NV4STRAPINFO); 570 and_out = *((uint8*)(&(rom[adress]))); 571 adress += 1; 572 byte = *((uint8*)(&(rom[adress]))); 573 adress += 1; 574 data &= (uint32)and_out; 575 LOG(8,("cmd 'CHK bits AND-out $%02x RAMCFG for $%02x'\n", 576 and_out, byte)); 577 if (((uint8)data) != byte) 578 { 579 LOG(8,("INFO: ---No match: not executing following command(s):\n")); 580 exec = false; 581 } 582 else 583 { 584 LOG(8,("INFO: ---Match, so this cmd has no effect.\n")); 585 } 586 break; 587 case 0x6e: 588 *size -= 13; 589 if (*size < 0) 590 { 591 LOG(8,("script size error, aborting!\n\n")); 592 end = true; 593 result = B_ERROR; 594 break; 595 } 596 597 /* execute */ 598 adress += 1; 599 reg = *((uint32*)(&(rom[adress]))); 600 adress += 4; 601 and_out = *((uint32*)(&(rom[adress]))); 602 adress += 4; 603 or_in = *((uint32*)(&(rom[adress]))); 604 adress += 4; 605 LOG(8,("cmd 'RD 32bit reg $%08x, AND-out = $%08x, OR-in = $%08x, WR-bk'\n", 606 reg, and_out, or_in)); 607 if (exec) 608 { 609 data = NV_REG32(reg); 610 data &= and_out; 611 data |= or_in; 612 NV_REG32(reg) = data; 613 } 614 break; 615 case 0x71: 616 LOG(8,("cmd 'END', execution completed.\n\n")); 617 end = true; 618 619 *size -= 1; 620 if (*size < 0) 621 { 622 LOG(8,("script size error!\n\n")); 623 result = B_ERROR; 624 } 625 break; 626 case 0x72: 627 *size -= 1; 628 if (*size < 0) 629 { 630 LOG(8,("script size error!\n\n")); 631 result = B_ERROR; 632 } 633 634 /* execute */ 635 adress += 1; 636 LOG(8,("cmd 'PGM commands'\n")); 637 LOG(8,("INFO: ---Executing following command(s):\n")); 638 exec = true; 639 break; 640 case 0x73: 641 *size -= 9; 642 if (*size < 0) 643 { 644 LOG(8,("script size error, aborting!\n\n")); 645 end = true; 646 result = B_ERROR; 647 break; 648 } 649 650 /* execute */ 651 adress += 1; 652 data = NV_REG32(NV32_NVSTRAPINFO2); 653 and_out = *((uint32*)(&(rom[adress]))); 654 adress += 4; 655 data2 = *((uint32*)(&(rom[adress]))); 656 adress += 4; 657 data &= and_out; 658 LOG(8,("cmd 'CHK bits AND-out $%08x STRAPCFG2 for $%08x'\n", 659 and_out, data2)); 660 if (data != data2) 661 { 662 LOG(8,("INFO: ---No match: not executing following command(s):\n")); 663 exec = false; 664 } 665 else 666 { 667 LOG(8,("INFO: ---Match, so this cmd has no effect.\n")); 668 } 669 break; 670 case 0x74: 671 *size -= 3; 672 if (*size < 0) 673 { 674 LOG(8,("script size error, aborting!\n\n")); 675 end = true; 676 result = B_ERROR; 677 break; 678 } 679 680 /* execute */ 681 adress += 1; 682 data = *((uint16*)(&(rom[adress]))); 683 adress += 2; 684 LOG(8,("cmd 'SNOOZE for %d ($%04x) microSeconds' (always done)\n", data, data)); 685 /* always done */ 686 snooze(data); 687 break; 688 case 0x77: 689 *size -= 7; 690 if (*size < 0) 691 { 692 LOG(8,("script size error, aborting!\n\n")); 693 end = true; 694 result = B_ERROR; 695 break; 696 } 697 698 /* execute */ 699 adress += 1; 700 reg = *((uint32*)(&(rom[adress]))); 701 adress += 4; 702 data = *((uint16*)(&(rom[adress]))); 703 adress += 2; 704 LOG(8,("cmd 'WR 32bit reg' $%08x = $%08x (b31-16 = '0', b15-0 = data)\n", 705 reg, data)); 706 if (exec) NV_REG32(reg) = data; 707 break; 708 case 0x78: 709 *size -= 6; 710 if (*size < 0) 711 { 712 LOG(8,("script size error, aborting!\n\n")); 713 end = true; 714 result = B_ERROR; 715 break; 716 } 717 718 /* execute */ 719 adress += 1; 720 reg = *((uint16*)(&(rom[adress]))); 721 adress += 2; 722 index = *((uint8*)(&(rom[adress]))); 723 adress += 1; 724 and_out = *((uint8*)(&(rom[adress]))); 725 adress += 1; 726 or_in = *((uint8*)(&(rom[adress]))); 727 adress += 1; 728 LOG(8,("cmd 'RD idx ISA reg $%02x via $%04x, AND-out = $%02x, OR-in = $%02x, WR-bk'\n", 729 index, reg, and_out, or_in)); 730 if (exec) 731 { 732 translate_ISA_PCI(®); 733 NV_REG8(reg) = index; 734 byte = NV_REG8(reg + 1); 735 byte &= (uint8)and_out; 736 byte |= (uint8)or_in; 737 NV_REG8(reg + 1) = byte; 738 } 739 break; 740 case 0x79: 741 *size -= 7; 742 if (*size < 0) 743 { 744 LOG(8,("script size error, aborting!\n\n")); 745 end = true; 746 result = B_ERROR; 747 break; 748 } 749 750 /* execute */ 751 adress += 1; 752 reg = *((uint32*)(&(rom[adress]))); 753 adress += 4; 754 data = *((uint16*)(&(rom[adress]))); 755 adress += 2; 756 LOG(8,("cmd 'calculate and set PLL 32bit reg $%08x for %.3fMHz'\n", reg, (data / 100.0))); 757 if (exec) 758 { 759 float calced_clk; 760 uint8 m, n, p; 761 nv_dac_sys_pll_find((data / 100.0), &calced_clk, &m, &n, &p, 0); 762 NV_REG32(reg) = ((p << 16) | (n << 8) | m); 763 } 764 log_pll(reg, (data / 100)); 765 break; 766 case 0x7a: 767 *size -= 9; 768 if (*size < 0) 769 { 770 LOG(8,("script size error, aborting!\n\n")); 771 end = true; 772 result = B_ERROR; 773 break; 774 } 775 776 /* execute */ 777 adress += 1; 778 reg = *((uint32*)(&(rom[adress]))); 779 adress += 4; 780 data = *((uint32*)(&(rom[adress]))); 781 adress += 4; 782 LOG(8,("cmd 'WR 32bit reg' $%08x = $%08x\n", reg, data)); 783 if (exec) NV_REG32(reg) = data; 784 break; 785 default: 786 LOG(8,("unknown cmd, aborting!\n\n")); 787 end = true; 788 result = B_ERROR; 789 break; 790 } 791 } 792 793 return result; 794} 795 796static void log_pll(uint32 reg, uint32 freq) 797{ 798 if ((si->ps.card_type == NV31) || (si->ps.card_type == NV36)) 799 LOG(8,("INFO: ---WARNING: check/update PLL programming script code!!!\n")); 800 switch (reg) 801 { 802 case NV32_MEMPLL: 803 LOG(8,("INFO: ---Memory PLL accessed.\n")); 804 /* update the card's specs */ 805 si->ps.std_memory_clock = freq; 806 break; 807 case NV32_COREPLL: 808 LOG(8,("INFO: ---Core PLL accessed.\n")); 809 /* update the card's specs */ 810 si->ps.std_engine_clock = freq; 811 break; 812 case NVDAC_PIXPLLC: 813 LOG(8,("INFO: ---DAC1 PLL accessed.\n")); 814 break; 815 case NVDAC2_PIXPLLC: 816 LOG(8,("INFO: ---DAC2 PLL accessed.\n")); 817 break; 818 /* unexpected cases, here for learning goals... */ 819 case NV32_MEMPLL2: 820 LOG(8,("INFO: ---NV31/NV36 extension to memory PLL accessed only!\n")); 821 break; 822 case NV32_COREPLL2: 823 LOG(8,("INFO: ---NV31/NV36 extension to core PLL accessed only!\n")); 824 break; 825 case NVDAC_PIXPLLC2: 826 LOG(8,("INFO: ---NV31/NV36 extension to DAC1 PLL accessed only!\n")); 827 break; 828 case NVDAC2_PIXPLLC2: 829 LOG(8,("INFO: ---NV31/NV36 extension to DAC2 PLL accessed only!\n")); 830 break; 831 default: 832 LOG(8,("INFO: ---Unknown PLL accessed!\n")); 833 break; 834 } 835} 836 837static void setup_ram_config(uint8* rom, uint16 ram_tab) 838{ 839 uint32 ram_cfg, data; 840 uint8 cnt; 841 842 /* set MRS = 256 */ 843 NV_REG32(NV32_PFB_DEBUG_0) &= 0xffffffef; 844 /* read RAM config hardware(?) strap */ 845 ram_cfg = ((NV_REG32(NV32_NVSTRAPINFO2) >> 2) & 0x0000000f); 846 LOG(8,("INFO: ---RAM config strap is $%01x\n", ram_cfg)); 847 /* use it as a pointer in a BIOS table for prerecorded RAM configurations */ 848 ram_cfg = *((uint16*)(&(rom[(ram_tab + (ram_cfg * 2))]))); 849 /* log info */ 850 switch (ram_cfg & 0x00000003) 851 { 852 case 0: 853 LOG(8,("INFO: ---32Mb RAM should be connected\n")); 854 break; 855 case 1: 856 LOG(8,("INFO: ---4Mb RAM should be connected\n")); 857 break; 858 case 2: 859 LOG(8,("INFO: ---8Mb RAM should be connected\n")); 860 break; 861 case 3: 862 LOG(8,("INFO: ---16Mb RAM should be connected\n")); 863 break; 864 } 865 if (ram_cfg & 0x00000004) 866 LOG(8,("INFO: ---RAM should be 128bits wide\n")); 867 else 868 LOG(8,("INFO: ---RAM should be 64bits wide\n")); 869 switch ((ram_cfg & 0x00000038) >> 3) 870 { 871 case 0: 872 LOG(8,("INFO: ---RAM type: 8Mbit SGRAM\n")); 873 break; 874 case 1: 875 LOG(8,("INFO: ---RAM type: 16Mbit SGRAM\n")); 876 break; 877 case 2: 878 LOG(8,("INFO: ---RAM type: 4 banks of 16Mbit SGRAM\n")); 879 break; 880 case 3: 881 LOG(8,("INFO: ---RAM type: 16Mbit SDRAM\n")); 882 break; 883 case 4: 884 LOG(8,("INFO: ---RAM type: 64Mbit SDRAM\n")); 885 break; 886 case 5: 887 LOG(8,("INFO: ---RAM type: 64Mbit x16 SDRAM\n")); 888 break; 889 } 890 /* set RAM amount, width and type */ 891 data = (NV_REG32(NV32_NV4STRAPINFO) & 0xffffffc0); 892 NV_REG32(NV32_NV4STRAPINFO) = (data | (ram_cfg & 0x0000003f)); 893 /* setup write to read delay (?) */ 894 data = (NV_REG32(NV32_PFB_CONFIG_1) & 0xff8ffffe); 895 data |= ((ram_cfg & 0x00000700) << 12); 896 /* force update via b0 = 0... */ 897 NV_REG32(NV32_PFB_CONFIG_1) = data; 898 /* ... followed by b0 = 1(?) */ 899 NV_REG32(NV32_PFB_CONFIG_1) = (data | 0x00000001); 900 901 /* do RAM width test to confirm RAM width set to be correct */ 902 /* write testpattern to first 128 bits of graphics memory... */ 903 data = 0x4e563541; 904 for (cnt = 0; cnt < 4; cnt++) 905 ((volatile uint32 *)si->framebuffer)[cnt] = data; 906 /* ... if second 64 bits does not contain the testpattern we are apparantly 907 * set to 128bits width while we should be set to 64bits width, so correct. */ 908 if (((volatile uint32 *)si->framebuffer)[3] != data) 909 { 910 LOG(8,("INFO: ---RAM width tested: width is 64bits, correcting settings.\n")); 911 NV_REG32(NV32_NV4STRAPINFO) &= ~0x00000004; 912 } 913 else 914 { 915 LOG(8,("INFO: ---RAM width tested: access is OK.\n")); 916 } 917 918 /* do RAM size test to confirm RAM size set to be correct */ 919 ram_cfg = (NV_REG32(NV32_NV4STRAPINFO) & 0x00000003); 920 data = 0x4e563542; 921 /* first check for 32Mb... */ 922 if (!ram_cfg) 923 { 924 /* write testpattern to just above the 16Mb boundary */ 925 ((volatile uint32 *)si->framebuffer)[(16 * 1024 * 1024) >> 2] = data; 926 /* check if pattern reads back */ 927 if (((volatile uint32 *)si->framebuffer)[(16 * 1024 * 1024) >> 2] == data) 928 { 929 /* write second testpattern to base adress */ 930 data = 0x4135564e; 931 ((volatile uint32 *)si->framebuffer)[0] = data; 932 if (((volatile uint32 *)si->framebuffer)[0] == data) 933 { 934 LOG(8,("INFO: ---RAM size tested: size was set OK (32Mb).\n")); 935 return; 936 } 937 } 938 /* one of the two tests for 32Mb failed, we must have 16Mb */ 939 ram_cfg = 0x00000003; 940 LOG(8,("INFO: ---RAM size tested: size is 16Mb, correcting settings.\n")); 941 NV_REG32(NV32_NV4STRAPINFO) = 942 (((NV_REG32(NV32_NV4STRAPINFO)) & 0xfffffffc) | ram_cfg); 943 return; 944 } 945 /* ... now check for 16Mb... */ 946 if (ram_cfg == 0x00000003) 947 { 948 /* increment testpattern */ 949 data++; 950 /* write testpattern to just above the 8Mb boundary */ 951 ((volatile uint32 *)si->framebuffer)[(8 * 1024 * 1024) >> 2] = data; 952 /* check if pattern reads back */ 953 if (((volatile uint32 *)si->framebuffer)[(8 * 1024 * 1024) >> 2] == data) 954 { 955 LOG(8,("INFO: ---RAM size tested: size was set OK (16Mb).\n")); 956 return; 957 } 958 else 959 { 960 /* assuming 8Mb: retesting below! */ 961 ram_cfg = 0x00000002; 962 LOG(8,("INFO: ---RAM size tested: size is NOT 16Mb, testing for 8Mb...\n")); 963 NV_REG32(NV32_NV4STRAPINFO) = 964 (((NV_REG32(NV32_NV4STRAPINFO)) & 0xfffffffc) | ram_cfg); 965 } 966 } 967 /* ... and now check for 8Mb! (ram_cfg will be 'pre'set to 4Mb or 8Mb here) */ 968 { 969 /* increment testpattern (again) */ 970 data++; 971 /* write testpattern to just above the 4Mb boundary */ 972 ((volatile uint32 *)si->framebuffer)[(4 * 1024 * 1024) >> 2] = data; 973 /* check if pattern reads back */ 974 if (((volatile uint32 *)si->framebuffer)[(4 * 1024 * 1024) >> 2] == data) 975 { 976 /* we have 8Mb, make sure this is set. */ 977 ram_cfg = 0x00000002; 978 LOG(8,("INFO: ---RAM size tested: size is 8Mb, setting 8Mb.\n")); 979 /* fixme? assuming this should be done here! */ 980 NV_REG32(NV32_NV4STRAPINFO) = 981 (((NV_REG32(NV32_NV4STRAPINFO)) & 0xfffffffc) | ram_cfg); 982 return; 983 } 984 else 985 { 986 /* we must have 4Mb, make sure this is set. */ 987 ram_cfg = 0x00000001; 988 LOG(8,("INFO: ---RAM size tested: size is 4Mb, setting 4Mb.\n")); 989 NV_REG32(NV32_NV4STRAPINFO) = 990 (((NV_REG32(NV32_NV4STRAPINFO)) & 0xfffffffc) | ram_cfg); 991 return; 992 } 993 } 994} 995 996/* this routine is used for NV10 and later */ 997static status_t exec_type2_script(uint8* rom, uint16 adress, int16* size, PinsTables tabs, uint16 ram_tab) 998{ 999 bool exec = true; 1000 1001 LOG(8,("\nINFO: executing type2 script at adress $%04x...\n", adress)); 1002 LOG(8,("INFO: ---Executing following command(s):\n")); 1003 1004 return exec_type2_script_mode(rom, &adress, size, tabs, ram_tab, &exec); 1005} 1006 1007/* this routine is used for NV10 and later. It's tested on a GeForce2 MX400 (NV11), 1008 * GeForce4 MX440 (NV18), GeForce4 Ti4200 (NV28) and a GeForceFX 5200 (NV34). 1009 * These cards coldstart perfectly. */ 1010static status_t exec_type2_script_mode(uint8* rom, uint16* adress, int16* size, PinsTables tabs, uint16 ram_tab, bool* exec) 1011{ 1012 status_t result = B_OK; 1013 bool end = false; 1014 uint8 index, byte, byte2, shift; 1015 uint32 reg, reg2, data, data2, and_out, and_out2, or_in, or_in2, safe32, offset32, size32; 1016 1017 while (!end) 1018 { 1019 LOG(8,("INFO: $%04x ($%02x); ", *adress, rom[*adress])); 1020 1021 /* all commands are here (verified NV11 and NV28) */ 1022 switch (rom[*adress]) 1023 { 1024 case 0x31: /* new */ 1025 *size -= (15 + ((*((uint8*)(&(rom[(*adress + 10)])))) << 2)); 1026 if (*size < 0) 1027 { 1028 LOG(8,("script size error, aborting!\n\n")); 1029 end = true; 1030 result = B_ERROR; 1031 break; 1032 } 1033 1034 /* execute */ 1035 *adress += 1; 1036 reg = *((uint32*)(&(rom[*adress]))); 1037 *adress += 4; 1038 and_out = *((uint32*)(&(rom[*adress]))); 1039 *adress += 4; 1040 shift = *((uint8*)(&(rom[*adress]))); 1041 *adress += 1; 1042 size32 = ((*((uint8*)(&(rom[*adress])))) << 2); 1043 *adress += 1; 1044 reg2 = *((uint32*)(&(rom[*adress]))); 1045 *adress += 4; 1046 LOG(8,("cmd 'RD 32bit reg $%08x, AND-out = $%08x, shift-right = $%02x,\n", 1047 reg, and_out, shift)); 1048 LOG(8,("INFO: (cont.) RD 32bit data from subtable with size $%04x, at offset (result << 2),\n", 1049 size32)); 1050 LOG(8,("INFO: (cont.) then WR result data to 32bit reg $%08x'\n", reg2)); 1051 if (*exec && reg2) 1052 { 1053 data = NV_REG32(reg); 1054 data &= and_out; 1055 data >>= shift; 1056 data2 = *((uint32*)(&(rom[(*adress + (data << 2))]))); 1057 NV_REG32(reg2) = data2; 1058 } 1059 *adress += size32; 1060 break; 1061 case 0x32: /* new */ 1062 *size -= (11 + ((*((uint8*)(&(rom[(*adress + 6)])))) << 2)); 1063 if (*size < 0) 1064 { 1065 LOG(8,("script size error, aborting!\n\n")); 1066 end = true; 1067 result = B_ERROR; 1068 break; 1069 } 1070 1071 /* execute */ 1072 *adress += 1; 1073 reg = *((uint16*)(&(rom[*adress]))); 1074 *adress += 2; 1075 index = *((uint8*)(&(rom[*adress]))); 1076 *adress += 1; 1077 and_out = *((uint8*)(&(rom[*adress]))); 1078 *adress += 1; 1079 byte2 = *((uint8*)(&(rom[*adress]))); 1080 *adress += 1; 1081 size32 = ((*((uint8*)(&(rom[*adress])))) << 2); 1082 *adress += 1; 1083 reg2 = *((uint32*)(&(rom[*adress]))); 1084 *adress += 4; 1085 LOG(8,("cmd 'RD idx ISA reg $%02x via $%04x, AND-out = $%02x, shift-right = $%02x,\n", 1086 index, reg, and_out, byte2)); 1087 LOG(8,("INFO: (cont.) RD 32bit data from subtable with size $%04x, at offset (result << 2),\n", 1088 size32)); 1089 LOG(8,("INFO: (cont.) then WR result data to 32bit reg $%08x'\n", reg2)); 1090 if (*exec && reg2) 1091 { 1092 translate_ISA_PCI(®); 1093 NV_REG8(reg) = index; 1094 byte = NV_REG8(reg + 1); 1095 byte &= (uint8)and_out; 1096 byte >>= byte2; 1097 offset32 = (byte << 2); 1098 data = *((uint32*)(&(rom[(*adress + offset32)]))); 1099 NV_REG32(reg2) = data; 1100 } 1101 *adress += size32; 1102 break; 1103 case 0x33: /* new */ 1104 *size -= 2; 1105 if (*size < 0) 1106 { 1107 LOG(8,("script size error, aborting!\n\n")); 1108 end = true; 1109 result = B_ERROR; 1110 break; 1111 } 1112 1113 /* execute */ 1114 *adress += 1; 1115 size32 = *((uint8*)(&(rom[*adress]))); 1116 *adress += 1; 1117 /* executed 1-256 times */ 1118 if (!size32) size32 = 256; 1119 /* remember where to start each time */ 1120 safe32 = *adress; 1121 LOG(8,("cmd 'execute following part of this script $%03x times' (always done)\n", size32)); 1122 for (offset32 = 0; offset32 < size32; offset32++) 1123 { 1124 LOG(8,("\nINFO: (#$%02x) executing part of type2 script at adress $%04x...\n", 1125 offset32, *adress)); 1126 LOG(8,("INFO: ---Not touching 'execution' mode at this time:\n")); 1127 *adress = safe32; 1128 result = exec_type2_script_mode(rom, adress, size, tabs, ram_tab, exec); 1129 } 1130 LOG(8,("INFO: ---Continuing script:\n")); 1131 break; 1132 case 0x34: /* new */ 1133 *size -= (12 + ((*((uint8*)(&(rom[(*adress + 7)])))) << 1)); 1134 if (*size < 0) 1135 { 1136 LOG(8,("script size error, aborting!\n\n")); 1137 end = true; 1138 result = B_ERROR; 1139 break; 1140 } 1141 1142 /* execute */ 1143 *adress += 1; 1144 reg = *((uint16*)(&(rom[*adress]))); 1145 *adress += 2; 1146 index = *((uint8*)(&(rom[*adress]))); 1147 *adress += 1; 1148 and_out = *((uint8*)(&(rom[*adress]))); 1149 *adress += 1; 1150 shift = *((uint8*)(&(rom[*adress]))); 1151 *adress += 1; 1152 offset32 = *((uint8*)(&(rom[*adress]))); 1153 *adress += 1; 1154 size32 = ((*((uint8*)(&(rom[*adress])))) << 1); 1155 *adress += 1; 1156 reg2 = *((uint32*)(&(rom[*adress]))); 1157 *adress += 4; 1158 LOG(8,("cmd 'RD idx ISA reg $%02x via $%04x, AND-out = $%02x, shift-right = $%02x,\n", 1159 index, reg, and_out, shift)); 1160 LOG(8,("INFO: (cont.) RD 16bit PLL frequency to pgm from subtable with size $%04x, at offset (result << 1),\n", 1161 size32)); 1162 LOG(8,("INFO: (cont.) RD table-index ($%02x) for cmd $39'\n", 1163 offset32)); 1164 translate_ISA_PCI(®); 1165 NV_REG8(reg) = index; 1166 byte = NV_REG8(reg + 1); 1167 byte &= (uint8)and_out; 1168 data = (byte >> shift); 1169 data <<= 1; 1170 data2 = *((uint16*)(&(rom[(*adress + data)]))); 1171 if (offset32 < 0x80) 1172 { 1173 bool double_f = true; 1174 LOG(8,("INFO: Do subcmd ($39); ")); 1175 exec_cmd_39_type2(rom, offset32, tabs, &double_f); 1176 LOG(8,("INFO: (cont. cmd $34) Doubling PLL frequency to be set for cmd $34.\n")); 1177 if (double_f) data2 <<= 1; 1178 LOG(8,("INFO: ---Reverting to pre-subcmd ($39) 'execution' mode.\n")); 1179 } 1180 else 1181 { 1182 LOG(8,("INFO: table index is negative, not executing subcmd ($39).\n")); 1183 } 1184 LOG(8,("INFO: (cont.) 'calc and set PLL 32bit reg $%08x for %.3fMHz'\n", 1185 reg2, (data2 / 100.0))); 1186 if (*exec && reg2) 1187 { 1188 float calced_clk; 1189 uint8 m, n, p; 1190 nv_dac_sys_pll_find((data2 / 100.0), &calced_clk, &m, &n, &p, 0); 1191 /* programming the PLL needs to be done in steps! (confirmed NV28) */ 1192 data = NV_REG32(reg2); 1193 NV_REG32(reg2) = ((data & 0xffff0000) | (n << 8) | m); 1194 data = NV_REG32(reg2); 1195 NV_REG32(reg2) = ((p << 16) | (n << 8) | m); 1196//fixme? 1197 /* program 2nd set N and M scalers if they exist (b31=1 enables them) */ 1198// if ((si->ps.card_type == NV31) || (si->ps.card_type == NV36)) 1199// DACW(PIXPLLC2, 0x80000401); 1200 } 1201 log_pll(reg2, (data2 / 100)); 1202 *adress += size32; 1203 break; 1204 case 0x35: /* new */ 1205 *size -= 2; 1206 if (*size < 0) 1207 { 1208 LOG(8,("script size error, aborting!\n\n")); 1209 end = true; 1210 result = B_ERROR; 1211 break; 1212 } 1213 1214 /* execute */ 1215 *adress += 1; 1216 byte = *((uint8*)(&(rom[*adress]))); 1217 *adress += 1; 1218 offset32 = (byte << 1); 1219 offset32 += tabs.InitFunctionTablePtr; 1220 LOG(8,("cmd 'execute fixed VGA BIOS routine #$%02x at adress $%04x'\n", 1221 byte, offset32)); 1222 /* note: 1223 * This command is BIOS/'pins' version specific. Confirmed a NV28 having NO 1224 * entries at all in InitFunctionTable! 1225 * (BIOS version 4.28.20.05.11; 'pins' version 5.21) */ 1226 //fixme: impl. if it turns out this cmd is used.. (didn't see that yet) 1227 if (*exec) 1228 { 1229 //fixme: add BIOS/'pins' version dependancy... 1230 switch(byte) 1231 { 1232 default: 1233 LOG(8,("\n\nINFO: WARNING: function not implemented, skipping!\n\n")); 1234 break; 1235 } 1236 } 1237 break; 1238 case 0x37: /* new */ 1239 *size -= 11; 1240 if (*size < 0) 1241 { 1242 LOG(8,("script size error, aborting!\n\n")); 1243 end = true; 1244 result = B_ERROR; 1245 break; 1246 } 1247 1248 /* execute */ 1249 *adress += 1; 1250 reg = *((uint32*)(&(rom[*adress]))); 1251 *adress += 4; 1252 byte2 = *((uint8*)(&(rom[*adress]))); 1253 *adress += 1; 1254 and_out = *((uint8*)(&(rom[*adress]))); 1255 *adress += 1; 1256 reg2 = *((uint16*)(&(rom[*adress]))); 1257 *adress += 2; 1258 index = *((uint8*)(&(rom[*adress]))); 1259 *adress += 1; 1260 and_out2 = *((uint8*)(&(rom[*adress]))); 1261 *adress += 1; 1262 LOG(8,("cmd 'RD 32bit reg $%08x, shift-right = $%02x, AND-out lsb = $%02x,\n", 1263 reg, byte2, and_out)); 1264 LOG(8,("INFO: (cont.) RD 8bit ISA reg $%02x via $%04x, AND-out = $%02x, OR-in lsb result 32bit, WR-bk'\n", 1265 index, reg2, and_out2)); 1266 if (*exec) 1267 { 1268 data = NV_REG32(reg); 1269 if (byte2 < 0x80) 1270 { 1271 data >>= byte2; 1272 } 1273 else 1274 { 1275 data <<= (0x0100 - byte2); 1276 } 1277 data &= and_out; 1278 translate_ISA_PCI(®2); 1279 NV_REG8(reg2) = index; 1280 byte = NV_REG8(reg2 + 1); 1281 byte &= (uint8)and_out2; 1282 byte |= (uint8)data; 1283 NV_REG8(reg2 + 1) = byte; 1284 } 1285 break; 1286 case 0x38: /* new */ 1287 *size -= 1; 1288 if (*size < 0) 1289 { 1290 LOG(8,("script size error, aborting!\n\n")); 1291 end = true; 1292 result = B_ERROR; 1293 break; 1294 } 1295 1296 /* execute */ 1297 *adress += 1; 1298 LOG(8,("cmd 'invert current mode'\n")); 1299 *exec = !(*exec); 1300 if (*exec) 1301 LOG(8,("INFO: ---Executing following command(s):\n")); 1302 else 1303 LOG(8,("INFO: ---Not executing following command(s):\n")); 1304 break; 1305 case 0x39: /* new */ 1306 *size -= 2; 1307 if (*size < 0) 1308 { 1309 LOG(8,("script size error, aborting!\n\n")); 1310 end = true; 1311 result = B_ERROR; 1312 break; 1313 } 1314 1315 /* execute */ 1316 *adress += 1; 1317 data = *((uint8*)(&(rom[*adress]))); 1318 *adress += 1; 1319 exec_cmd_39_type2(rom, data, tabs, exec); 1320 break; 1321 case 0x49: /* new */ 1322 size32 = *((uint8*)(&(rom[*adress + 17]))); 1323 if (!size32) size32 = 256; 1324 *size -= (18 + (size32 << 1)); 1325 if (*size < 0) 1326 { 1327 LOG(8,("script size error, aborting!\n\n")); 1328 end = true; 1329 result = B_ERROR; 1330 break; 1331 } 1332 1333 /* execute */ 1334 *adress += 1; 1335 reg = *((uint32*)(&(rom[*adress]))); 1336 *adress += 4; 1337 reg2 = *((uint32*)(&(rom[*adress]))); 1338 *adress += 4; 1339 and_out = *((uint32*)(&(rom[*adress]))); 1340 *adress += 4; 1341 or_in = *((uint32*)(&(rom[*adress]))); 1342 *adress += 4; 1343 size32 = *((uint8*)(&(rom[*adress]))); 1344 if (!size32) size32 = 256; 1345 *adress += 1; 1346 LOG(8,("cmd 'do following cmd structure $%03x time(s)':\n", size32)); 1347 for (offset32 = 0; offset32 < size32; offset32++) 1348 { 1349 or_in2 = *((uint8*)(&(rom[(*adress + (offset32 << 1))]))); 1350 data2 = *((uint8*)(&(rom[(*adress + (offset32 << 1) + 1)]))); 1351 LOG(8,("INFO (cont.) (#$%02x) cmd 'WR 32bit reg $%08x = $%08x, RD 32bit reg $%08x,\n", 1352 offset32, reg2, data2, reg)); 1353 LOG(8,("INFO (cont.) AND-out $%08x, OR-in $%08x, OR-in $%08x, WR-bk'\n", 1354 and_out, or_in, or_in2)); 1355 } 1356 if (*exec) 1357 { 1358 for (index = 0; index < size32; index++) 1359 { 1360 or_in2 = *((uint8*)(&(rom[*adress]))); 1361 *adress += 1; 1362 data2 = *((uint8*)(&(rom[*adress]))); 1363 *adress += 1; 1364 NV_REG32(reg2) = data2; 1365 data = NV_REG32(reg); 1366 data &= and_out; 1367 data |= or_in; 1368 data |= or_in2; 1369 NV_REG32(reg) = data; 1370 } 1371 } 1372 else 1373 { 1374 *adress += (size32 << 1); 1375 } 1376 break; 1377 case 0x61: /* new */ 1378 *size -= 4; 1379 if (*size < 0) 1380 { 1381 LOG(8,("script size error, aborting!\n\n")); 1382 end = true; 1383 result = B_ERROR; 1384 break; 1385 } 1386 1387 /* execute */ 1388 *adress += 1; 1389 reg = *((uint16*)(&(rom[*adress]))); 1390 *adress += 2; 1391 byte = *((uint8*)(&(rom[*adress]))); 1392 *adress += 1; 1393 LOG(8,("cmd 'WR ISA reg $%04x = $%02x'\n", reg, byte)); 1394 if (*exec) 1395 { 1396 translate_ISA_PCI(®); 1397 NV_REG8(reg) = byte; 1398 } 1399 break; 1400 case 0x62: /* new */ 1401 *size -= 5; 1402 if (*size < 0) 1403 { 1404 LOG(8,("script size error, aborting!\n\n")); 1405 end = true; 1406 result = B_ERROR; 1407 break; 1408 } 1409 1410 /* execute */ 1411 *adress += 1; 1412 reg = *((uint16*)(&(rom[*adress]))); 1413 *adress += 2; 1414 index = *((uint8*)(&(rom[*adress]))); 1415 *adress += 1; 1416 byte = *((uint8*)(&(rom[*adress]))); 1417 *adress += 1; 1418 LOG(8,("cmd 'WR idx ISA reg $%02x via $%04x = $%02x'\n", index, reg, byte)); 1419 if (*exec) 1420 { 1421 translate_ISA_PCI(®); 1422 NV_REG16(reg) = ((((uint16)byte) << 8) | index); 1423 } 1424 break; 1425 case 0x63: /* new setup compared to pre-NV10 version */ 1426 *size -= 1; 1427 if (*size < 0) 1428 { 1429 LOG(8,("script size error, aborting!\n\n")); 1430 end = true; 1431 result = B_ERROR; 1432 break; 1433 } 1434 1435 /* execute */ 1436 *adress += 1; 1437 LOG(8,("cmd 'setup RAM config' (always done)\n")); 1438 /* always done */ 1439 switch (si->ps.card_type) 1440 { 1441 case NV28: 1442 setup_ram_config_nv28(rom); 1443 break; 1444 default: 1445 setup_ram_config_nv10_up(rom); 1446 break; 1447 } 1448 break; 1449 case 0x65: /* identical to type1 */ 1450 *size -= 13; 1451 if (*size < 0) 1452 { 1453 LOG(8,("script size error, aborting!\n\n")); 1454 end = true; 1455 result = B_ERROR; 1456 break; 1457 } 1458 1459 /* execute */ 1460 *adress += 1; 1461 reg = *((uint32*)(&(rom[*adress]))); 1462 *adress += 4; 1463 data = *((uint32*)(&(rom[*adress]))); 1464 *adress += 4; 1465 data2 = *((uint32*)(&(rom[*adress]))); 1466 *adress += 4; 1467 LOG(8,("cmd 'WR 32bit reg $%08x = $%08x, then = $%08x' (always done)\n", 1468 reg, data, data2)); 1469 /* always done */ 1470 NV_REG32(reg) = data; 1471 NV_REG32(reg) = data2; 1472 CFGW(ROMSHADOW, (CFGR(ROMSHADOW) & 0xfffffffe)); 1473 break; 1474 case 0x69: /* identical to type1 */ 1475 *size -= 5; 1476 if (*size < 0) 1477 { 1478 LOG(8,("script size error, aborting!\n\n")); 1479 end = true; 1480 result = B_ERROR; 1481 break; 1482 } 1483 1484 /* execute */ 1485 *adress += 1; 1486 reg = *((uint16*)(&(rom[*adress]))); 1487 *adress += 2; 1488 and_out = *((uint8*)(&(rom[*adress]))); 1489 *adress += 1; 1490 or_in = *((uint8*)(&(rom[*adress]))); 1491 *adress += 1; 1492 LOG(8,("cmd 'RD 8bit ISA reg $%04x, AND-out = $%02x, OR-in = $%02x, WR-bk'\n", 1493 reg, and_out, or_in)); 1494 if (*exec) 1495 { 1496 translate_ISA_PCI(®); 1497 byte = NV_REG8(reg); 1498 byte &= (uint8)and_out; 1499 byte |= (uint8)or_in; 1500 NV_REG8(reg) = byte; 1501 } 1502 break; 1503 case 0x6a: /* new */ 1504 *size -= 2; 1505 if (*size < 0) 1506 { 1507 LOG(8,("script size error, aborting!\n\n")); 1508 end = true; 1509 result = B_ERROR; 1510 break; 1511 } 1512 1513 /* execute */ 1514 *adress += 1; 1515 data = *((uint8*)(&(rom[*adress]))); 1516 *adress += 1; 1517 data2 = *((uint16*)(&(rom[(tabs.InitScriptTablePtr + (data << 1))]))); 1518 LOG(8,("cmd 'jump to script #$%02x at adress $%04x'\n", data, data2)); 1519 if (*exec) 1520 { 1521 *adress = data2; 1522 LOG(8,("INFO: ---Jumping; not touching 'execution' mode.\n")); 1523 } 1524 break; 1525 case 0x6b: /* new */ 1526 *size -= 2; 1527 if (*size < 0) 1528 { 1529 LOG(8,("script size error, aborting!\n\n")); 1530 end = true; 1531 result = B_ERROR; 1532 break; 1533 } 1534 1535 /* execute */ 1536 *adress += 1; 1537 data = *((uint8*)(&(rom[*adress]))); 1538 *adress += 1; 1539 data2 = *((uint16*)(&(rom[(tabs.InitScriptTablePtr + (data << 1))]))); 1540 LOG(8,("cmd 'gosub script #$%02x at adress $%04x'\n", data, data2)); 1541 if (*exec && data2) 1542 { 1543 result = exec_type2_script(rom, data2, size, tabs, ram_tab); 1544 LOG(8,("INFO: ---Reverting to pre-gosub 'execution' mode.\n")); 1545 } 1546 break; 1547 case 0x6e: /* identical to type1 */ 1548 *size -= 13; 1549 if (*size < 0) 1550 { 1551 LOG(8,("script size error, aborting!\n\n")); 1552 end = true; 1553 result = B_ERROR; 1554 break; 1555 } 1556 1557 /* execute */ 1558 *adress += 1; 1559 reg = *((uint32*)(&(rom[*adress]))); 1560 *adress += 4; 1561 and_out = *((uint32*)(&(rom[*adress]))); 1562 *adress += 4; 1563 or_in = *((uint32*)(&(rom[*adress]))); 1564 *adress += 4; 1565 LOG(8,("cmd 'RD 32bit reg $%08x, AND-out = $%08x, OR-in = $%08x, WR-bk'\n", 1566 reg, and_out, or_in)); 1567 if (*exec) 1568 { 1569 data = NV_REG32(reg); 1570 data &= and_out; 1571 data |= or_in; 1572 NV_REG32(reg) = data; 1573 } 1574 break; 1575 case 0x6f: /* new */ 1576 *size -= 2; 1577 if (*size < 0) 1578 { 1579 LOG(8,("script size error, aborting!\n\n")); 1580 end = true; 1581 result = B_ERROR; 1582 break; 1583 } 1584 1585 /* execute */ 1586 *adress += 1; 1587 byte = *((uint8*)(&(rom[*adress]))); 1588 *adress += 1; 1589 data = tabs.MacroIndexTablePtr + (byte << 1); 1590 offset32 = (*((uint8*)(&(rom[data]))) << 3); 1591 size32 = *((uint8*)(&(rom[(data + 1)]))); 1592 offset32 += tabs.MacroTablePtr; 1593 /* note: min 1, max 255 commands can be requested */ 1594 LOG(8,("cmd 'do $%02x time(s) a 32bit reg WR with 32bit data' (MacroIndexTable idx = $%02x):\n", 1595 size32, byte)); 1596 safe32 = 0; 1597 while (safe32 < size32) 1598 { 1599 reg2 = *((uint32*)(&(rom[(offset32 + (safe32 << 3))]))); 1600 data2 = *((uint32*)(&(rom[(offset32 + (safe32 << 3) + 4)]))); 1601 LOG(8,("INFO: (cont.) (#$%02x) cmd 'WR 32bit reg' $%08x = $%08x\n", 1602 safe32, reg2, data2)); 1603 safe32++; 1604 } 1605 if (*exec) 1606 { 1607 safe32 = 0; 1608 while (safe32 < size32) 1609 { 1610 reg2 = *((uint32*)(&(rom[(offset32 + (safe32 << 3))]))); 1611 data2 = *((uint32*)(&(rom[(offset32 + (safe32 << 3) + 4)]))); 1612 NV_REG32(reg2) = data2; 1613 safe32++; 1614 } 1615 } 1616 break; 1617 case 0x36: /* new */ 1618 case 0x66: /* new */ 1619 case 0x67: /* new */ 1620 case 0x68: /* new */ 1621 case 0x6c: /* new */ 1622 case 0x71: /* identical to type1 */ 1623 LOG(8,("cmd 'END', execution completed.\n\n")); 1624 end = true; 1625 1626 *size -= 1; 1627 if (*size < 0) 1628 { 1629 LOG(8,("script size error!\n\n")); 1630 result = B_ERROR; 1631 } 1632 1633 /* execute */ 1634 *adress += 1; /* needed to make cmd #$33 work correctly! */ 1635 break; 1636 case 0x72: /* identical to type1 */ 1637 *size -= 1; 1638 if (*size < 0) 1639 { 1640 LOG(8,("script size error!\n\n")); 1641 result = B_ERROR; 1642 } 1643 1644 /* execute */ 1645 *adress += 1; 1646 LOG(8,("cmd 'PGM commands'\n")); 1647 LOG(8,("INFO: ---Executing following command(s):\n")); 1648 *exec = true; 1649 break; 1650 case 0x74: /* identical to type1 */ 1651 //fixme? on at least NV28 this cmd hammers the CRTC PCI-timeout register 1652 //'data' number of times instead of snoozing. 1653 //Couldn't see any diff in behaviour though! 1654 *size -= 3; 1655 if (*size < 0) 1656 { 1657 LOG(8,("script size error, aborting!\n\n")); 1658 end = true; 1659 result = B_ERROR; 1660 break; 1661 } 1662 1663 /* execute */ 1664 *adress += 1; 1665 data = *((uint16*)(&(rom[*adress]))); 1666 *adress += 2; 1667 LOG(8,("cmd 'SNOOZE for %d ($%04x) microSeconds' (always done)\n", data, data)); 1668 /* always done */ 1669 snooze(data); 1670 break; 1671 case 0x75: /* new */ 1672 *size -= 2; 1673 if (*size < 0) 1674 { 1675 LOG(8,("script size error!\n\n")); 1676 result = B_ERROR; 1677 } 1678 1679 /* execute */ 1680 *adress += 1; 1681 data = *((uint8*)(&(rom[*adress]))); 1682 *adress += 1; 1683 data *= 12; 1684 data += tabs.ConditionTablePtr; 1685 reg = *((uint32*)(&(rom[data]))); 1686 and_out = *((uint32*)(&(rom[(data + 4)]))); 1687 data2 = *((uint32*)(&(rom[(data + 8)]))); 1688 data = NV_REG32(reg); 1689 data &= and_out; 1690 LOG(8,("cmd 'CHK bits AND-out $%08x reg $%08x for $%08x'\n", 1691 and_out, reg, data2)); 1692 if (data != data2) 1693 { 1694 LOG(8,("INFO: ---No match: not executing following command(s):\n")); 1695 *exec = false; 1696 } 1697 else 1698 { 1699 LOG(8,("INFO: ---Match, so this cmd has no effect.\n")); 1700 } 1701 break; 1702 case 0x76: /* new */ 1703 *size -= 2; 1704 if (*size < 0) 1705 { 1706 LOG(8,("script size error!\n\n")); 1707 result = B_ERROR; 1708 } 1709 1710 /* execute */ 1711 *adress += 1; 1712 data = *((uint8*)(&(rom[*adress]))); 1713 *adress += 1; 1714 data *= 5; 1715 data += tabs.IOConditionTablePtr; 1716 reg = *((uint16*)(&(rom[data]))); 1717 index = *((uint8*)(&(rom[(data + 2)]))); 1718 and_out = *((uint8*)(&(rom[(data + 3)]))); 1719 byte2 = *((uint8*)(&(rom[(data + 4)]))); 1720 LOG(8,("cmd 'CHK bits AND-out $%02x idx ISA reg $%02x via $%04x for $%02x'\n", 1721 and_out, index, reg, byte2)); 1722 translate_ISA_PCI(®); 1723 NV_REG8(reg) = index; 1724 byte = NV_REG8(reg + 1); 1725 byte &= (uint8)and_out; 1726 if (byte != byte2) 1727 { 1728 LOG(8,("INFO: ---No match: not executing following command(s):\n")); 1729 *exec = false; 1730 } 1731 else 1732 { 1733 LOG(8,("INFO: ---Match, so this cmd has no effect.\n")); 1734 } 1735 break; 1736 case 0x78: /* identical to type1 */ 1737 *size -= 6; 1738 if (*size < 0) 1739 { 1740 LOG(8,("script size error, aborting!\n\n")); 1741 end = true; 1742 result = B_ERROR; 1743 break; 1744 } 1745 1746 /* execute */ 1747 *adress += 1; 1748 reg = *((uint16*)(&(rom[*adress]))); 1749 *adress += 2; 1750 index = *((uint8*)(&(rom[*adress]))); 1751 *adress += 1; 1752 and_out = *((uint8*)(&(rom[*adress]))); 1753 *adress += 1; 1754 or_in = *((uint8*)(&(rom[*adress]))); 1755 *adress += 1; 1756 LOG(8,("cmd 'RD idx ISA reg $%02x via $%04x, AND-out = $%02x, OR-in = $%02x, WR-bk'\n", 1757 index, reg, and_out, or_in)); 1758 if (*exec) 1759 { 1760 translate_ISA_PCI(®); 1761 NV_REG8(reg) = index; 1762 byte = NV_REG8(reg + 1); 1763 byte &= (uint8)and_out; 1764 byte |= (uint8)or_in; 1765 NV_REG8(reg + 1) = byte; 1766 } 1767 break; 1768 case 0x79: 1769 *size -= 7; 1770 if (*size < 0) 1771 { 1772 LOG(8,("script size error, aborting!\n\n")); 1773 end = true; 1774 result = B_ERROR; 1775 break; 1776 } 1777 1778 /* execute */ 1779 *adress += 1; 1780 reg = *((uint32*)(&(rom[*adress]))); 1781 *adress += 4; 1782 data = *((uint16*)(&(rom[*adress]))); 1783 *adress += 2; 1784 LOG(8,("cmd 'calculate and set PLL 32bit reg $%08x for %.3fMHz'\n", reg, (data / 100.0))); 1785 if (*exec) 1786 { 1787 float calced_clk; 1788 uint8 m, n, p; 1789 nv_dac_sys_pll_find((data / 100.0), &calced_clk, &m, &n, &p, 0); 1790 /* programming the PLL needs to be done in steps! (confirmed NV28) */ 1791 data2 = NV_REG32(reg); 1792 NV_REG32(reg) = ((data2 & 0xffff0000) | (n << 8) | m); 1793 data2 = NV_REG32(reg); 1794 NV_REG32(reg) = ((p << 16) | (n << 8) | m); 1795//fixme? 1796 /* program 2nd set N and M scalers if they exist (b31=1 enables them) */ 1797// if ((si->ps.card_type == NV31) || (si->ps.card_type == NV36)) 1798// DACW(PIXPLLC2, 0x80000401); 1799 } 1800 log_pll(reg, (data / 100)); 1801 break; 1802 case 0x7a: /* identical to type1 */ 1803 *size -= 9; 1804 if (*size < 0) 1805 { 1806 LOG(8,("script size error, aborting!\n\n")); 1807 end = true; 1808 result = B_ERROR; 1809 break; 1810 } 1811 1812 /* execute */ 1813 *adress += 1; 1814 reg = *((uint32*)(&(rom[*adress]))); 1815 *adress += 4; 1816 data = *((uint32*)(&(rom[*adress]))); 1817 *adress += 4; 1818 LOG(8,("cmd 'WR 32bit reg' $%08x = $%08x\n", reg, data)); 1819 if (*exec) NV_REG32(reg) = data; 1820 break; 1821 default: 1822 LOG(8,("unknown cmd, aborting!\n\n")); 1823 end = true; 1824 result = B_ERROR; 1825 break; 1826 } 1827 } 1828 1829 return result; 1830} 1831 1832static void exec_cmd_39_type2(uint8* rom, uint32 data, PinsTables tabs, bool* exec) 1833{ 1834 uint8 index, byte, byte2, safe, shift; 1835 uint32 reg, and_out, and_out2, offset32; 1836 1837 data *= 9; 1838 data += tabs.IOFlagConditionTablePtr; 1839 reg = *((uint16*)(&(rom[data]))); 1840 index = *((uint8*)(&(rom[(data + 2)]))); 1841 and_out = *((uint8*)(&(rom[(data + 3)]))); 1842 shift = *((uint8*)(&(rom[(data + 4)]))); 1843 offset32 = *((uint16*)(&(rom[data + 5]))); 1844 and_out2 = *((uint8*)(&(rom[(data + 7)]))); 1845 byte2 = *((uint8*)(&(rom[(data + 8)]))); 1846 LOG(8,("cmd 'AND-out bits $%02x idx ISA reg $%02x via $%04x, shift-right = $%02x,\n", 1847 and_out, index, reg, shift)); 1848 translate_ISA_PCI(®); 1849 NV_REG8(reg) = index; 1850 byte = NV_REG8(reg + 1); 1851 byte &= (uint8)and_out; 1852 offset32 += (byte >> shift); 1853 safe = byte = *((uint8*)(&(rom[offset32]))); 1854 byte &= (uint8)and_out2; 1855 LOG(8,("INFO: (cont.) use result as index in table to get data $%02x,\n", 1856 safe)); 1857 LOG(8,("INFO: (cont.) then chk bits AND-out $%02x of data for $%02x'\n", 1858 and_out2, byte2)); 1859 if (byte != byte2) 1860 { 1861 LOG(8,("INFO: ---No match: not executing following command(s):\n")); 1862 *exec = false; 1863 } 1864 else 1865 { 1866 LOG(8,("INFO: ---Match, so this cmd has no effect.\n")); 1867 } 1868} 1869 1870static void setup_ram_config_nv10_up(uint8* rom) 1871{ 1872 /* note: 1873 * After writing data to RAM a snooze is required to make the test work. 1874 * Confirmed a NV11: without snooze it worked OK on a low-voltage AGP2.0 slot, 1875 * but on a higher-voltage AGP 1.0 slot it failed to identify errors correctly!! 1876 * Adding the snooze fixed that. */ 1877 1878 uint32 data, dummy; 1879 uint8 cnt = 0; 1880 status_t stat = B_ERROR; 1881 1882 /* set 'refctrl is valid' */ 1883 NV_REG32(NV32_PFB_REFCTRL) = 0x80000000; 1884 1885 /* check RAM for 256bits buswidth(?) */ 1886 while ((cnt < 4) && (stat != B_OK)) 1887 { 1888 /* reset RAM bits at offset 224-255 bits four times */ 1889 ((volatile uint32 *)si->framebuffer)[0x07] = 0x00000000; 1890 snooze(10); 1891 ((volatile uint32 *)si->framebuffer)[0x07] = 0x00000000; 1892 snooze(10); 1893 ((volatile uint32 *)si->framebuffer)[0x07] = 0x00000000; 1894 snooze(10); 1895 ((volatile uint32 *)si->framebuffer)[0x07] = 0x00000000; 1896 snooze(10); 1897 /* write testpattern */ 1898 ((volatile uint32 *)si->framebuffer)[0x07] = 0x4e563131; 1899 snooze(10); 1900 /* reset RAM bits at offset 480-511 bits */ 1901 ((volatile uint32 *)si->framebuffer)[0x0f] = 0x00000000; 1902 snooze(10); 1903 /* check testpattern to have survived */ 1904 if (((volatile uint32 *)si->framebuffer)[0x07] == 0x4e563131) stat = B_OK; 1905 cnt++; 1906 } 1907 1908 /* if pattern did not hold modify RAM-type setup */ 1909 if (stat != B_OK) 1910 { 1911 LOG(8,("INFO: ---RAM test #1 done: access errors, modified setup.\n")); 1912 data = NV_REG32(NV32_PFB_CONFIG_0); 1913 if (data & 0x00000010) 1914 { 1915 data &= 0xffffffcf; 1916 } 1917 else 1918 { 1919 data &= 0xffffffcf; 1920 data |= 0x00000020; 1921 } 1922 NV_REG32(NV32_PFB_CONFIG_0) = data; 1923 } 1924 else 1925 { 1926 LOG(8,("INFO: ---RAM test #1 done: access is OK.\n")); 1927 } 1928 1929 /* check RAM bankswitching stuff(?) */ 1930 cnt = 0; 1931 stat = B_ERROR; 1932 while ((cnt < 4) && (stat != B_OK)) 1933 { 1934 /* read RAM size */ 1935 data = NV_REG32(NV32_NV10STRAPINFO); 1936 /* subtract 1MB */ 1937 data -= 0x00100000; 1938 /* write testpattern at generated RAM adress */ 1939 ((volatile uint32 *)si->framebuffer)[(data >> 2)] = 0x4e564441; 1940 snooze(10); 1941 /* reset first RAM adress */ 1942 ((volatile uint32 *)si->framebuffer)[0x00] = 0x00000000; 1943 snooze(10); 1944 /* dummyread first RAM adress four times */ 1945 dummy = ((volatile uint32 *)si->framebuffer)[0x00]; 1946 dummy = ((volatile uint32 *)si->framebuffer)[0x00]; 1947 dummy = ((volatile uint32 *)si->framebuffer)[0x00]; 1948 dummy = ((volatile uint32 *)si->framebuffer)[0x00]; 1949 /* check testpattern to have survived */ 1950 if (((volatile uint32 *)si->framebuffer)[(data >> 2)] == 0x4e564441) stat = B_OK; 1951 cnt++; 1952 } 1953 1954 /* if pattern did not hold modify RAM-type setup */ 1955 if (stat != B_OK) 1956 { 1957 LOG(8,("INFO: ---RAM test #2 done: access errors, modified setup.\n")); 1958 NV_REG32(NV32_PFB_CONFIG_0) &= 0xffffefff; 1959 } 1960 else 1961 { 1962 LOG(8,("INFO: ---RAM test #2 done: access is OK.\n")); 1963 } 1964} 1965 1966/* Note: this routine assumes at least 128Mb was mapped to memory (kerneldriver). 1967 * It doesn't matter if the card actually _has_ this amount of RAM or not(!) */ 1968static void setup_ram_config_nv28(uint8* rom) 1969{ 1970 /* note: 1971 * After writing data to RAM a snooze is required to make the test work. 1972 * Confirmed a NV11: without snooze it worked OK on a low-voltage AGP2.0 slot, 1973 * but on a higher-voltage AGP 1.0 slot it failed to identify errors correctly!! 1974 * Adding the snooze fixed that. */ 1975 1976 uint32 dummy; 1977 uint8 cnt = 0; 1978 status_t stat = B_ERROR; 1979 1980 /* set 'refctrl is valid' */ 1981 NV_REG32(NV32_PFB_REFCTRL) = 0x80000000; 1982 1983 /* check RAM */ 1984 while ((cnt < 4) && (stat != B_OK)) 1985 { 1986 /* set bit 11: 'pulse' something into a new setting? */ 1987 NV_REG32(NV32_PFB_CONFIG_0) |= 0x00000800; 1988 /* write testpattern to RAM adress 127Mb */ 1989 ((volatile uint32 *)si->framebuffer)[0x01fc0000] = 0x4e564441; 1990 snooze(10); 1991 /* reset first RAM adress */ 1992 ((volatile uint32 *)si->framebuffer)[0x00000000] = 0x00000000; 1993 snooze(10); 1994 /* dummyread first RAM adress four times */ 1995 dummy = ((volatile uint32 *)si->framebuffer)[0x00000000]; 1996 LOG(8,("INFO: (#%d) dummy1 = $%08x, ", cnt, dummy)); 1997 dummy = ((volatile uint32 *)si->framebuffer)[0x00000000]; 1998 LOG(8,("dummy2 = $%08x, ", dummy)); 1999 dummy = ((volatile uint32 *)si->framebuffer)[0x00000000]; 2000 LOG(8,("dummy3 = $%08x, ", dummy)); 2001 dummy = ((volatile uint32 *)si->framebuffer)[0x00000000]; 2002 LOG(8,("dummy4 = $%08x\n", dummy)); 2003 /* check testpattern to have survived */ 2004 if (((volatile uint32 *)si->framebuffer)[0x01fc0000] == 0x4e564441) stat = B_OK; 2005 cnt++; 2006 } 2007 2008 /* clear bit 11: set normal mode */ 2009 NV_REG32(NV32_PFB_CONFIG_0) &= ~0x00000800; 2010 2011 if (stat == B_OK) 2012 LOG(8,("INFO: ---RAM test done: access was OK within %d iteration(s).\n", cnt)); 2013 else 2014 LOG(8,("INFO: ---RAM test done: access was still not OK after 4 iterations.\n")); 2015} 2016 2017static status_t translate_ISA_PCI(uint32* reg) 2018{ 2019 switch (*reg) 2020 { 2021 case 0x03c0: 2022 *reg = NV8_ATTRDATW; 2023 break; 2024 case 0x03c1: 2025 *reg = NV8_ATTRDATR; 2026 break; 2027 case 0x03c2: 2028 *reg = NV8_MISCW; 2029 break; 2030 case 0x03c4: 2031 *reg = NV8_SEQIND; 2032 break; 2033 case 0x03c5: 2034 *reg = NV8_SEQDAT; 2035 break; 2036 case 0x03c6: 2037 *reg = NV8_PALMASK; 2038 break; 2039 case 0x03c7: 2040 *reg = NV8_PALINDR; 2041 break; 2042 case 0x03c8: 2043 *reg = NV8_PALINDW; 2044 break; 2045 case 0x03c9: 2046 *reg = NV8_PALDATA; 2047 break; 2048 case 0x03cc: 2049 *reg = NV8_MISCR; 2050 break; 2051 case 0x03ce: 2052 *reg = NV8_GRPHIND; 2053 break; 2054 case 0x03cf: 2055 *reg = NV8_GRPHDAT; 2056 break; 2057 case 0x03d4: 2058 *reg = NV8_CRTCIND; 2059 break; 2060 case 0x03d5: 2061 *reg = NV8_CRTCDAT; 2062 break; 2063 case 0x03da: 2064 *reg = NV8_INSTAT1; 2065 break; 2066 default: 2067 LOG(8,("\n\nINFO: WARNING: ISA->PCI register adress translation failed!\n\n")); 2068 return B_ERROR; 2069 break; 2070 } 2071 2072 return B_OK; 2073} 2074 2075void set_pll(uint32 reg, uint32 req_clk) 2076{ 2077 uint32 data; 2078 float calced_clk; 2079 uint8 m, n, p; 2080 nv_dac_sys_pll_find(req_clk, &calced_clk, &m, &n, &p, 0); 2081 /* programming the PLL needs to be done in steps! (confirmed NV28) */ 2082 data = NV_REG32(reg); 2083 NV_REG32(reg) = ((data & 0xffff0000) | (n << 8) | m); 2084 data = NV_REG32(reg); 2085 NV_REG32(reg) = ((p << 16) | (n << 8) | m); 2086 2087//fixme? 2088 /* program 2nd set N and M scalers if they exist (b31=1 enables them) */ 2089 if (si->ps.ext_pll) 2090 { 2091 if (reg == NV32_COREPLL) NV_REG32(NV32_COREPLL2) = 0x80000401; 2092 if (reg == NV32_MEMPLL) NV_REG32(NV32_MEMPLL2) = 0x80000401; 2093 } 2094 2095 log_pll(reg, req_clk); 2096} 2097 2098/* doing general fail-safe default setup here */ 2099static status_t nv_crtc_setup_fifo() 2100{ 2101 /* enable access to primary head */ 2102 set_crtc_owner(0); 2103 2104 /* set CRTC FIFO burst size to 256 */ 2105 CRTCW(FIFO, 0x03); 2106 2107 /* set CRTC FIFO low watermark to 32 */ 2108 CRTCW(FIFO_LWM, 0x20); 2109 2110 return B_OK; 2111} 2112 2113/* (pre)set 'fixed' card specifications */ 2114void set_specs(void) 2115{ 2116 LOG(8,("INFO: setting up card specifications\n")); 2117 2118 /* set failsave speeds */ 2119 switch (si->ps.card_type) 2120 { 2121 case NV04: 2122 pinsnv4_fake(); 2123 break; 2124 case NV05: 2125 case NV05M64: 2126 pinsnv5_nv5m64_fake(); 2127 break; 2128 case NV06: 2129 pinsnv6_fake(); 2130 break; 2131 default: 2132 switch (si->ps.card_arch) 2133 { 2134 case NV10A: 2135 pinsnv10_arch_fake(); 2136 break; 2137 case NV20A: 2138 pinsnv20_arch_fake(); 2139 break; 2140 case NV30A: 2141 case NV40A: 2142 pinsnv30_arch_fake(); 2143 break; 2144 default: 2145 /* 'failsafe' values... */ 2146 pinsnv10_arch_fake(); 2147 break; 2148 } 2149 break; 2150 } 2151 2152 /* detect reference crystal frequency and dualhead */ 2153 switch (si->ps.card_arch) 2154 { 2155 case NV04A: 2156 getstrap_arch_nv4(); 2157 break; 2158 default: 2159 getstrap_arch_nv10_20_30_40(); 2160 break; 2161 } 2162} 2163 2164/* this routine presumes the card was coldstarted by the card's BIOS for panel stuff */ 2165void fake_panel_start(void) 2166{ 2167 LOG(8,("INFO: detecting RAM size\n")); 2168 2169 /* detect RAM amount */ 2170 switch (si->ps.card_arch) 2171 { 2172 case NV04A: 2173 getRAMsize_arch_nv4(); 2174 break; 2175 default: 2176 getRAMsize_arch_nv10_20_30_40(); 2177 break; 2178 } 2179 2180 /* override memory detection if requested by user */ 2181 if (si->settings.memory != 0) 2182 { 2183 LOG(2,("INFO: forcing memory size (specified in settings file)\n")); 2184 si->ps.memory_size = si->settings.memory * 1024 * 1024; 2185 } 2186 2187 /* find out if the card has a tvout chip */ 2188 si->ps.tvout = false; 2189 si->ps.tv_encoder.type = NONE; 2190 si->ps.tv_encoder.version = 0; 2191 /* I2C init currently also fetches DDC EDID info from all connected screens */ 2192 i2c_init(); 2193 //fixme: add support for more encoders... 2194 BT_probe(); 2195 2196 LOG(8,("INFO: faking panel startup\n")); 2197 2198 /* find out the BIOS preprogrammed panel use status... */ 2199 detect_panels(); 2200 2201 /* determine and setup output devices and heads */ 2202 setup_output_matrix(); 2203 2204 /* select other CRTC for primary head use if specified by user in settings file */ 2205 if (si->ps.secondary_head && si->settings.switchhead) 2206 { 2207 LOG(2,("INFO: inverting head use (specified in nvidia.settings file)\n")); 2208 si->ps.crtc2_prim = !si->ps.crtc2_prim; 2209 } 2210} 2211 2212/* notes: 2213 * - Since laptops don't have edid for their internal panels, and we can't switch 2214 * digitally connected external panels to DAC's, we keep needing the info fetched 2215 * from card programming done by the cardBIOS. 2216 * - Because we can only output modes on digitally connected panels upto/including 2217 * the modeline programmed into the GPU by the cardBIOS we don't use the actual 2218 * native modelines fetched via EDID for digitally connected panels. 2219 * - If the BIOS didn't program a modeline in the GPU for a digitally connected panel 2220 * we can't use that panel. 2221 * - The above restrictions exist due to missing nVidia hardware specs. */ 2222static void detect_panels() 2223{ 2224 /* detect if the BIOS enabled LCD's (internal panels or DVI) or TVout */ 2225 2226 /* both external TMDS transmitters (used for LCD/DVI) and external TVencoders 2227 * (can) use the CRTC's in slaved mode. */ 2228 /* Note: 2229 * DFP's are programmed with standard VESA modelines by the card's BIOS! */ 2230 bool slaved_for_dev1 = false, slaved_for_dev2 = false; 2231 bool tvout1 = false, tvout2 = false; 2232 2233 /* check primary head: */ 2234 /* enable access to primary head */ 2235 set_crtc_owner(0); 2236 2237 /* unlock head's registers for R/W access */ 2238 CRTCW(LOCK, 0x57); 2239 CRTCW(VSYNCE ,(CRTCR(VSYNCE) & 0x7f)); 2240 2241 LOG(2,("INFO: Dumping flatpanel related CRTC registers:\n")); 2242 /* related info PIXEL register: 2243 * b7: 1 = slaved mode (all cards). */ 2244 LOG(2,("CRTC1: PIXEL register: $%02x\n", CRTCR(PIXEL))); 2245 /* info LCD register: 2246 * b7: 1 = stereo view (shutter glasses use) (all cards), 2247 * b5: 1 = power ext. TMDS (or something)/0 = TVout use (?) (confirmed NV17, NV28), 2248 * b4: 1 = power ext. TMDS (or something)/0 = TVout use (?) (confirmed NV34), 2249 * b3: 1 = ??? (not panel related probably!) (confirmed NV34), 2250 * b1: 1 = power ext. TMDS (or something) (?) (confirmed NV05?, NV17), 2251 * b0: 1 = select panel encoder / 0 = select TVout encoder (all cards). */ 2252 LOG(2,("CRTC1: LCD register: $%02x\n", CRTCR(LCD))); 2253 /* info 0x59 register: 2254 * b0: 1 = enable ext. TMDS clock (DPMS) (confirmed NV28, NV34). */ 2255 LOG(2,("CRTC1: register $59: $%02x\n", CRTCR(0x59))); 2256 /* info 0x9f register: 2257 * b4: 0 = TVout use (?). */ 2258 LOG(2,("CRTC1: register $9f: $%02x\n", CRTCR(0x9f))); 2259 2260 /* detect active slave device (if any) */ 2261 slaved_for_dev1 = (CRTCR(PIXEL) & 0x80); 2262 if (slaved_for_dev1) 2263 { 2264 /* if the panel isn't selected, tvout is.. */ 2265 tvout1 = !(CRTCR(LCD) & 0x01); 2266 } 2267 2268 if (si->ps.secondary_head) 2269 { 2270 /* check secondary head: */ 2271 /* enable access to secondary head */ 2272 set_crtc_owner(1); 2273 /* unlock head's registers for R/W access */ 2274 CRTC2W(LOCK, 0x57); 2275 CRTC2W(VSYNCE ,(CRTC2R(VSYNCE) & 0x7f)); 2276 2277 LOG(2,("CRTC2: PIXEL register: $%02x\n", CRTC2R(PIXEL))); 2278 LOG(2,("CRTC2: LCD register: $%02x\n", CRTC2R(LCD))); 2279 LOG(2,("CRTC2: register $59: $%02x\n", CRTC2R(0x59))); 2280 LOG(2,("CRTC2: register $9f: $%02x\n", CRTC2R(0x9f))); 2281 2282 /* detect active slave device (if any) */ 2283 slaved_for_dev2 = (CRTC2R(PIXEL) & 0x80); 2284 if (slaved_for_dev2) 2285 { 2286 /* if the panel isn't selected, tvout is.. */ 2287 tvout2 = !(CRTC2R(LCD) & 0x01); 2288 } 2289 } 2290 2291 LOG(2,("INFO: End flatpanel related CRTC registers dump.\n")); 2292 2293 /* do some presets */ 2294 si->ps.p1_timing.h_display = 0; 2295 si->ps.p1_timing.v_display = 0; 2296 si->ps.p2_timing.h_display = 0; 2297 si->ps.p2_timing.v_display = 0; 2298 si->ps.slaved_tmds1 = false; 2299 si->ps.slaved_tmds2 = false; 2300 si->ps.master_tmds1 = false; 2301 si->ps.master_tmds2 = false; 2302 si->ps.monitors = 0x00; 2303 /* determine the situation we are in... (regarding flatpanels) */ 2304 /* fixme: add VESA DDC EDID stuff one day... */ 2305 /* fixme: find out how to program those transmitters one day instead of 2306 * relying on the cards BIOS to do it. This adds TVout options where panels 2307 * are used! 2308 * Currently we'd loose the panel setup while not being able to restore it. */ 2309 2310 /* note: (facts) 2311 * -> NV11 and NV17 laptops have LVDS panels, programmed in both sets registers; 2312 * -> NV34 laptops have TMDS panels, programmed in only one set of registers; 2313 * -> NV11, NV25 and NV34 DVI cards, so external panels (TMDS) are programmed 2314 * in only one set of registers; 2315 * -> a register-set's FP_TG_CTRL register, bit 31 tells you if a LVDS panel is 2316 * connected to the primary head (0), or to the secondary head (1) except 2317 * on some NV11's if this bit is '0' there; 2318 * -> for LVDS panels both registersets are programmed identically by the card's 2319 * BIOSes; 2320 * -> the programmed set of registers tells you where a TMDS (DVI) panel is 2321 * connected; 2322 * -> On all cards a CRTC is used in slaved mode when a panel is connected, 2323 * except on NV11: here master mode is (might be?) detected. */ 2324 /* note also: 2325 * external TMDS encoders are only used for logic-level translation: it's 2326 * modeline registers are not used. Instead the GPU's internal modeline registers 2327 * are used. The external encoder is not connected to a I2C bus (confirmed NV34). */ 2328 if (slaved_for_dev1 && !tvout1) 2329 { 2330 uint16 width = ((DACR(FP_HDISPEND) & 0x0000ffff) + 1); 2331 uint16 height = ((DACR(FP_VDISPEND) & 0x0000ffff) + 1); 2332 if ((width >= 640) && (height >= 480)) 2333 { 2334 si->ps.slaved_tmds1 = true; 2335 si->ps.monitors |= CRTC1_TMDS; 2336 si->ps.p1_timing.h_display = width; 2337 si->ps.p1_timing.v_display = height; 2338 } 2339 } 2340 2341 if (si->ps.secondary_head && slaved_for_dev2 && !tvout2) 2342 { 2343 uint16 width = ((DAC2R(FP_HDISPEND) & 0x0000ffff) + 1); 2344 uint16 height = ((DAC2R(FP_VDISPEND) & 0x0000ffff) + 1); 2345 if ((width >= 640) && (height >= 480)) 2346 { 2347 si->ps.slaved_tmds2 = true; 2348 si->ps.monitors |= CRTC2_TMDS; 2349 si->ps.p2_timing.h_display = width; 2350 si->ps.p2_timing.v_display = height; 2351 } 2352 } 2353 2354 if ((si->ps.card_type == NV11) && 2355 !si->ps.slaved_tmds1 && !tvout1) 2356 { 2357 uint16 width = ((DACR(FP_HDISPEND) & 0x0000ffff) + 1); 2358 uint16 height = ((DACR(FP_VDISPEND) & 0x0000ffff) + 1); 2359 if ((width >= 640) && (height >= 480)) 2360 { 2361 si->ps.master_tmds1 = true; 2362 si->ps.monitors |= CRTC1_TMDS; 2363 si->ps.p1_timing.h_display = width; 2364 si->ps.p1_timing.v_display = height; 2365 } 2366 } 2367 2368 if ((si->ps.card_type == NV11) && 2369 si->ps.secondary_head && !si->ps.slaved_tmds2 && !tvout2) 2370 { 2371 uint16 width = ((DAC2R(FP_HDISPEND) & 0x0000ffff) + 1); 2372 uint16 height = ((DAC2R(FP_VDISPEND) & 0x0000ffff) + 1); 2373 if ((width >= 640) && (height >= 480)) 2374 { 2375 si->ps.master_tmds2 = true; 2376 si->ps.monitors |= CRTC2_TMDS; 2377 si->ps.p2_timing.h_display = width; 2378 si->ps.p2_timing.v_display = height; 2379 } 2380 } 2381 2382 //fixme...: 2383 //we are assuming that no DVI is used as external monitor on laptops; 2384 //otherwise we probably get into trouble here if the checked specs match. 2385 if (si->ps.laptop && 2386 ((si->ps.monitors & (CRTC1_TMDS | CRTC2_TMDS)) == (CRTC1_TMDS | CRTC2_TMDS)) && 2387 ((DACR(FP_TG_CTRL) & 0x80000000) == (DAC2R(FP_TG_CTRL) & 0x80000000)) && 2388 (si->ps.p1_timing.h_display == si->ps.p2_timing.h_display) && 2389 (si->ps.p1_timing.v_display == si->ps.p2_timing.v_display)) 2390 { 2391 LOG(2,("INFO: correcting double detection of single panel!\n")); 2392 2393 if (si->ps.card_type == NV11) 2394 { 2395 /* LVDS panel is _always_ on CRTC2, so clear false primary detection */ 2396 si->ps.slaved_tmds1 = false; 2397 si->ps.master_tmds1 = false; 2398 si->ps.monitors &= ~CRTC1_TMDS; 2399 si->ps.p1_timing.h_display = 0; 2400 si->ps.p1_timing.v_display = 0; 2401 } 2402 else 2403 { 2404 if (DACR(FP_TG_CTRL) & 0x80000000) 2405 { 2406 /* LVDS panel is on CRTC2, so clear false primary detection */ 2407 si->ps.slaved_tmds1 = false; 2408 si->ps.master_tmds1 = false; 2409 si->ps.monitors &= ~CRTC1_TMDS; 2410 si->ps.p1_timing.h_display = 0; 2411 si->ps.p1_timing.v_display = 0; 2412 } 2413 else 2414 { 2415 /* LVDS panel is on CRTC1, so clear false secondary detection */ 2416 si->ps.slaved_tmds2 = false; 2417 si->ps.master_tmds2 = false; 2418 si->ps.monitors &= ~CRTC2_TMDS; 2419 si->ps.p2_timing.h_display = 0; 2420 si->ps.p2_timing.v_display = 0; 2421 } 2422 } 2423 } 2424 2425 /* fetch panel(s) modeline(s) */ 2426 if (si->ps.monitors & CRTC1_TMDS) 2427 { 2428 /* horizontal timing */ 2429 si->ps.p1_timing.h_sync_start = (DACR(FP_HSYNC_S) & 0x0000ffff) + 1; 2430 si->ps.p1_timing.h_sync_end = (DACR(FP_HSYNC_E) & 0x0000ffff) + 1; 2431 si->ps.p1_timing.h_total = (DACR(FP_HTOTAL) & 0x0000ffff) + 1; 2432 /* vertical timing */ 2433 si->ps.p1_timing.v_sync_start = (DACR(FP_VSYNC_S) & 0x0000ffff) + 1; 2434 si->ps.p1_timing.v_sync_end = (DACR(FP_VSYNC_E) & 0x0000ffff) + 1; 2435 si->ps.p1_timing.v_total = (DACR(FP_VTOTAL) & 0x0000ffff) + 1; 2436 /* sync polarity */ 2437 si->ps.p1_timing.flags = 0; 2438 if (DACR(FP_TG_CTRL) & 0x00000001) si->ps.p1_timing.flags |= B_POSITIVE_VSYNC; 2439 if (DACR(FP_TG_CTRL) & 0x00000010) si->ps.p1_timing.flags |= B_POSITIVE_HSYNC; 2440 /* display enable polarity (not an official flag) */ 2441 if (DACR(FP_TG_CTRL) & 0x10000000) si->ps.p1_timing.flags |= B_BLANK_PEDESTAL; 2442 /* refreshrate: 2443 * fix a DVI or laptop flatpanel to 60Hz refresh! */ 2444 si->ps.p1_timing.pixel_clock = 2445 (si->ps.p1_timing.h_total * si->ps.p1_timing.v_total * 60) / 1000; 2446 } 2447 if (si->ps.monitors & CRTC2_TMDS) 2448 { 2449 /* horizontal timing */ 2450 si->ps.p2_timing.h_sync_start = (DAC2R(FP_HSYNC_S) & 0x0000ffff) + 1; 2451 si->ps.p2_timing.h_sync_end = (DAC2R(FP_HSYNC_E) & 0x0000ffff) + 1; 2452 si->ps.p2_timing.h_total = (DAC2R(FP_HTOTAL) & 0x0000ffff) + 1; 2453 /* vertical timing */ 2454 si->ps.p2_timing.v_sync_start = (DAC2R(FP_VSYNC_S) & 0x0000ffff) + 1; 2455 si->ps.p2_timing.v_sync_end = (DAC2R(FP_VSYNC_E) & 0x0000ffff) + 1; 2456 si->ps.p2_timing.v_total = (DAC2R(FP_VTOTAL) & 0x0000ffff) + 1; 2457 /* sync polarity */ 2458 si->ps.p2_timing.flags = 0; 2459 if (DAC2R(FP_TG_CTRL) & 0x00000001) si->ps.p2_timing.flags |= B_POSITIVE_VSYNC; 2460 if (DAC2R(FP_TG_CTRL) & 0x00000010) si->ps.p2_timing.flags |= B_POSITIVE_HSYNC; 2461 /* display enable polarity (not an official flag) */ 2462 if (DAC2R(FP_TG_CTRL) & 0x10000000) si->ps.p2_timing.flags |= B_BLANK_PEDESTAL; 2463 /* refreshrate: 2464 * fix a DVI or laptop flatpanel to 60Hz refresh! */ 2465 si->ps.p2_timing.pixel_clock = 2466 (si->ps.p2_timing.h_total * si->ps.p2_timing.v_total * 60) / 1000; 2467 } 2468 2469 /* dump some panel configuration registers... */ 2470 LOG(2,("INFO: Dumping flatpanel registers:\n")); 2471 LOG(2,("DUALHEAD_CTRL: $%08x\n", NV_REG32(NV32_DUALHEAD_CTRL))); 2472 LOG(2,("DAC1: FP_HDISPEND: %d\n", DACR(FP_HDISPEND))); 2473 LOG(2,("DAC1: FP_HTOTAL: %d\n", DACR(FP_HTOTAL))); 2474 LOG(2,("DAC1: FP_HCRTC: %d\n", DACR(FP_HCRTC))); 2475 LOG(2,("DAC1: FP_HSYNC_S: %d\n", DACR(FP_HSYNC_S))); 2476 LOG(2,("DAC1: FP_HSYNC_E: %d\n", DACR(FP_HSYNC_E))); 2477 LOG(2,("DAC1: FP_HVALID_S: %d\n", DACR(FP_HVALID_S))); 2478 LOG(2,("DAC1: FP_HVALID_E: %d\n", DACR(FP_HVALID_E))); 2479 2480 LOG(2,("DAC1: FP_VDISPEND: %d\n", DACR(FP_VDISPEND))); 2481 LOG(2,("DAC1: FP_VTOTAL: %d\n", DACR(FP_VTOTAL))); 2482 LOG(2,("DAC1: FP_VCRTC: %d\n", DACR(FP_VCRTC))); 2483 LOG(2,("DAC1: FP_VSYNC_S: %d\n", DACR(FP_VSYNC_S))); 2484 LOG(2,("DAC1: FP_VSYNC_E: %d\n", DACR(FP_VSYNC_E))); 2485 LOG(2,("DAC1: FP_VVALID_S: %d\n", DACR(FP_VVALID_S))); 2486 LOG(2,("DAC1: FP_VVALID_E: %d\n", DACR(FP_VVALID_E))); 2487 2488 LOG(2,("DAC1: FP_CHKSUM: $%08x = (dec) %d\n", DACR(FP_CHKSUM),DACR(FP_CHKSUM))); 2489 LOG(2,("DAC1: FP_TST_CTRL: $%08x\n", DACR(FP_TST_CTRL))); 2490 LOG(2,("DAC1: FP_TG_CTRL: $%08x\n", DACR(FP_TG_CTRL))); 2491 LOG(2,("DAC1: FP_DEBUG0: $%08x\n", DACR(FP_DEBUG0))); 2492 LOG(2,("DAC1: FP_DEBUG1: $%08x\n", DACR(FP_DEBUG1))); 2493 LOG(2,("DAC1: FP_DEBUG2: $%08x\n", DACR(FP_DEBUG2))); 2494 LOG(2,("DAC1: FP_DEBUG3: $%08x\n", DACR(FP_DEBUG3))); 2495 2496 LOG(2,("DAC1: FUNCSEL: $%08x\n", NV_REG32(NV32_FUNCSEL))); 2497 LOG(2,("DAC1: PANEL_PWR: $%08x\n", NV_REG32(NV32_PANEL_PWR))); 2498 2499 if(si->ps.secondary_head) 2500 { 2501 LOG(2,("DAC2: FP_HDISPEND: %d\n", DAC2R(FP_HDISPEND))); 2502 LOG(2,("DAC2: FP_HTOTAL: %d\n", DAC2R(FP_HTOTAL))); 2503 LOG(2,("DAC2: FP_HCRTC: %d\n", DAC2R(FP_HCRTC))); 2504 LOG(2,("DAC2: FP_HSYNC_S: %d\n", DAC2R(FP_HSYNC_S))); 2505 LOG(2,("DAC2: FP_HSYNC_E: %d\n", DAC2R(FP_HSYNC_E))); 2506 LOG(2,("DAC2: FP_HVALID_S:%d\n", DAC2R(FP_HVALID_S))); 2507 LOG(2,("DAC2: FP_HVALID_E: %d\n", DAC2R(FP_HVALID_E))); 2508 2509 LOG(2,("DAC2: FP_VDISPEND: %d\n", DAC2R(FP_VDISPEND))); 2510 LOG(2,("DAC2: FP_VTOTAL: %d\n", DAC2R(FP_VTOTAL))); 2511 LOG(2,("DAC2: FP_VCRTC: %d\n", DAC2R(FP_VCRTC))); 2512 LOG(2,("DAC2: FP_VSYNC_S: %d\n", DAC2R(FP_VSYNC_S))); 2513 LOG(2,("DAC2: FP_VSYNC_E: %d\n", DAC2R(FP_VSYNC_E))); 2514 LOG(2,("DAC2: FP_VVALID_S: %d\n", DAC2R(FP_VVALID_S))); 2515 LOG(2,("DAC2: FP_VVALID_E: %d\n", DAC2R(FP_VVALID_E))); 2516 2517 LOG(2,("DAC2: FP_CHKSUM: $%08x = (dec) %d\n", DAC2R(FP_CHKSUM),DAC2R(FP_CHKSUM))); 2518 LOG(2,("DAC2: FP_TST_CTRL: $%08x\n", DAC2R(FP_TST_CTRL))); 2519 LOG(2,("DAC2: FP_TG_CTRL: $%08x\n", DAC2R(FP_TG_CTRL))); 2520 LOG(2,("DAC2: FP_DEBUG0: $%08x\n", DAC2R(FP_DEBUG0))); 2521 LOG(2,("DAC2: FP_DEBUG1: $%08x\n", DAC2R(FP_DEBUG1))); 2522 LOG(2,("DAC2: FP_DEBUG2: $%08x\n", DAC2R(FP_DEBUG2))); 2523 LOG(2,("DAC2: FP_DEBUG3: $%08x\n", DAC2R(FP_DEBUG3))); 2524 2525 LOG(2,("DAC2: FUNCSEL: $%08x\n", NV_REG32(NV32_2FUNCSEL))); 2526 LOG(2,("DAC2: PANEL_PWR: $%08x\n", NV_REG32(NV32_2PANEL_PWR))); 2527 } 2528 2529 /* if something goes wrong during driver init reading those registers below might 2530 * result in a hanging system. Without reading them at least a blind (or KDL) 2531 * restart becomes possible. Leaving the code here for debugging purposes. */ 2532 if (0) { 2533 /* determine flatpanel type(s) */ 2534 /* note: 2535 * - on NV11 accessing registerset(s) hangs card. 2536 * - the same applies for NV34. 2537 * Confirmed for DAC2 access on ID 0x0322, 2538 * but only after a failed VESA modeswitch by the HAIKU kernel 2539 * at boot time caused by a BIOS fault inside the gfx card: it says 2540 * it can do VESA 1280x1024x32 on CRTC1/DAC1 but it fails: no signal. */ 2541 if ((si->ps.monitors & CRTC1_TMDS) && (si->ps.card_type != NV11)) 2542 { 2543 /* Read a indexed register to see if it indicates LVDS or TMDS panel presence. 2544 * b0-7 = adress, b16 = 1 = write_enable */ 2545 DACW(FP_TMDS_CTRL, ((1 << 16) | 0x04)); 2546 /* (b0-7 = data) */ 2547 if (DACR(FP_TMDS_DATA) & 0x01) 2548 LOG(2,("INFO: Flatpanel on head 1 is LVDS type\n")); 2549 else 2550 LOG(2,("INFO: Flatpanel on head 1 is TMDS type\n")); 2551 } 2552 if ((si->ps.monitors & CRTC2_TMDS) && (si->ps.card_type != NV11)) 2553 { 2554 /* Read a indexed register to see if it indicates LVDS or TMDS panel presence. 2555 * b0-7 = adress, b16 = 1 = write_enable */ 2556 DAC2W(FP_TMDS_CTRL, ((1 << 16) | 0x04)); 2557 /* (b0-7 = data) */ 2558 if (DAC2R(FP_TMDS_DATA) & 0x01) 2559 LOG(2,("INFO: Flatpanel on head 2 is LVDS type\n")); 2560 else 2561 LOG(2,("INFO: Flatpanel on head 2 is TMDS type\n")); 2562 } 2563 } 2564 2565 LOG(2,("INFO: End flatpanel registers dump.\n")); 2566} 2567 2568static void setup_output_matrix() 2569{ 2570 /* setup defaults: */ 2571 /* head 1 will be the primary head */ 2572 si->ps.crtc2_prim = false; 2573 /* no screens usable */ 2574 si->ps.crtc1_screen.have_native_edid = false; 2575 si->ps.crtc1_screen.have_full_edid = false; 2576 si->ps.crtc1_screen.timing.h_display = 0; 2577 si->ps.crtc1_screen.timing.v_display = 0; 2578 si->ps.crtc2_screen.have_native_edid = false; 2579 si->ps.crtc2_screen.have_full_edid = false; 2580 si->ps.crtc2_screen.timing.h_display = 0; 2581 si->ps.crtc2_screen.timing.v_display = 0; 2582 2583 /* connect analog outputs straight through if possible */ 2584 if ((si->ps.secondary_head) && (si->ps.card_type != NV11)) 2585 nv_general_output_select(false); 2586 2587 /* panels are pre-connected to a CRTC (1 or 2) by the card's BIOS, 2588 * we can't change this (lack of info) */ 2589 2590 /* detect analog monitors. First try EDID, else use load sensing. */ 2591 /* (load sensing is confirmed working OK on NV04, NV05, NV11, NV18, NV28 and NV34.) */ 2592 /* primary connector: */ 2593 if (si->ps.con1_screen.have_native_edid) { 2594 if (!si->ps.con1_screen.digital) si->ps.monitors |= CRTC1_VGA; 2595 } else { 2596 if (nv_dac_crt_connected()) { 2597 si->ps.monitors |= CRTC1_VGA; 2598 /* assume 4:3 monitor on con1 */ 2599 si->ps.con1_screen.aspect = 1.33; 2600 } 2601 } 2602 2603 /* Note: digitally connected panels take precedence over analog connected screens. */ 2604 2605 /* fill-out crtc1_screen. This is tricky since we don't know which connector connects 2606 * to crtc1. 2607 * Also the BIOS might have programmed for a lower mode than EDID reports: 2608 * which limits our use of the panel (LVDS link setup too slow). */ 2609 if(si->ps.monitors & CRTC1_TMDS) { 2610 /* see if we have the full EDID info somewhere (lacking a hardware spec so 2611 * we need to compare: we don't know the location of a digital cross switch. 2612 * Note: don't compare pixelclock and flags as we make them up ourselves!) */ 2613 if (si->ps.con1_screen.have_full_edid && si->ps.con1_screen.digital && 2614 (si->ps.p1_timing.h_display == si->ps.con1_screen.timing.h_display) && 2615 (si->ps.p1_timing.h_sync_start == si->ps.con1_screen.timing.h_sync_start) && 2616 (si->ps.p1_timing.h_sync_end == si->ps.con1_screen.timing.h_sync_end) && 2617 (si->ps.p1_timing.h_total == si->ps.con1_screen.timing.h_total) && 2618 (si->ps.p1_timing.v_display == si->ps.con1_screen.timing.v_display) && 2619 (si->ps.p1_timing.v_sync_start == si->ps.con1_screen.timing.v_sync_start) && 2620 (si->ps.p1_timing.v_sync_end == si->ps.con1_screen.timing.v_sync_end) && 2621 (si->ps.p1_timing.v_total == si->ps.con1_screen.timing.v_total)) { 2622 /* fill-out crtc1_screen from EDID info fetched from connector 1 */ 2623 memcpy(&(si->ps.crtc1_screen), &(si->ps.con1_screen), sizeof(si->ps.crtc1_screen)); 2624 } else { 2625 if (si->ps.con2_screen.have_full_edid && si->ps.con2_screen.digital && 2626 (si->ps.p1_timing.h_display == si->ps.con2_screen.timing.h_display) && 2627 (si->ps.p1_timing.h_sync_start == si->ps.con2_screen.timing.h_sync_start) && 2628 (si->ps.p1_timing.h_sync_end == si->ps.con2_screen.timing.h_sync_end) && 2629 (si->ps.p1_timing.h_total == si->ps.con2_screen.timing.h_total) && 2630 (si->ps.p1_timing.v_display == si->ps.con2_screen.timing.v_display) && 2631 (si->ps.p1_timing.v_sync_start == si->ps.con2_screen.timing.v_sync_start) && 2632 (si->ps.p1_timing.v_sync_end == si->ps.con2_screen.timing.v_sync_end) && 2633 (si->ps.p1_timing.v_total == si->ps.con2_screen.timing.v_total)) { 2634 /* fill-out crtc1_screen from EDID info fetched from connector 2 */ 2635 memcpy(&(si->ps.crtc1_screen), &(si->ps.con2_screen), sizeof(si->ps.crtc1_screen)); 2636 } else { 2637 /* no match or no full EDID info: use the info fetched from the GPU */ 2638 si->ps.crtc1_screen.timing.pixel_clock = si->ps.p1_timing.pixel_clock; 2639 si->ps.crtc1_screen.timing.h_display = si->ps.p1_timing.h_display; 2640 si->ps.crtc1_screen.timing.h_sync_start = si->ps.p1_timing.h_sync_start; 2641 si->ps.crtc1_screen.timing.h_sync_end = si->ps.p1_timing.h_sync_end; 2642 si->ps.crtc1_screen.timing.h_total = si->ps.p1_timing.h_total; 2643 si->ps.crtc1_screen.timing.v_display = si->ps.p1_timing.v_display; 2644 si->ps.crtc1_screen.timing.v_sync_start = si->ps.p1_timing.v_sync_start; 2645 si->ps.crtc1_screen.timing.v_sync_end = si->ps.p1_timing.v_sync_end; 2646 si->ps.crtc1_screen.timing.v_total = si->ps.p1_timing.v_total; 2647 si->ps.crtc1_screen.timing.flags = si->ps.p1_timing.flags; 2648 si->ps.crtc1_screen.have_native_edid = true; 2649 si->ps.crtc1_screen.aspect = 2650 (si->ps.p1_timing.h_display / ((float)si->ps.p1_timing.v_display)); 2651 si->ps.crtc1_screen.digital = true; 2652 } 2653 } 2654 } else if(si->ps.monitors & CRTC1_VGA) { 2655 /* fill-out crtc1_screen from EDID info, or faked info if EDID failed. */ 2656 memcpy(&(si->ps.crtc1_screen), &(si->ps.con1_screen), sizeof(si->ps.crtc1_screen)); 2657 } 2658 2659 /* force widescreen types if requested */ 2660 if (si->settings.force_ws) si->ps.crtc1_screen.aspect = 1.78; 2661 2662 /* setup output devices and heads */ 2663 if (si->ps.secondary_head) 2664 { 2665 /* fill-out crtc2_screen. This is tricky since we don't know which connector 2666 * connects to crtc2. 2667 * Also the BIOS might have programmed for a lower mode than EDID reports: 2668 * which limits our use of the panel (LVDS link setup too slow). */ 2669 if(si->ps.monitors & CRTC2_TMDS) { 2670 /* see if we have the full EDID info somewhere (lacking a hardware spec so 2671 * we need to compare: we don't know the location of a digital cross switch. 2672 * Note: don't compare pixelclock and flags as we make them up ourselves!) */ 2673 if (si->ps.con1_screen.have_full_edid && si->ps.con1_screen.digital && 2674 (si->ps.p2_timing.h_display == si->ps.con1_screen.timing.h_display) && 2675 (si->ps.p2_timing.h_sync_start == si->ps.con1_screen.timing.h_sync_start) && 2676 (si->ps.p2_timing.h_sync_end == si->ps.con1_screen.timing.h_sync_end) && 2677 (si->ps.p2_timing.h_total == si->ps.con1_screen.timing.h_total) && 2678 (si->ps.p2_timing.v_display == si->ps.con1_screen.timing.v_display) && 2679 (si->ps.p2_timing.v_sync_start == si->ps.con1_screen.timing.v_sync_start) && 2680 (si->ps.p2_timing.v_sync_end == si->ps.con1_screen.timing.v_sync_end) && 2681 (si->ps.p2_timing.v_total == si->ps.con1_screen.timing.v_total)) { 2682 /* fill-out crtc2_screen from EDID info fetched from connector 1 */ 2683 memcpy(&(si->ps.crtc2_screen), &(si->ps.con1_screen), sizeof(si->ps.crtc2_screen)); 2684 } else { 2685 if (si->ps.con2_screen.have_full_edid && si->ps.con2_screen.digital && 2686 (si->ps.p2_timing.h_display == si->ps.con2_screen.timing.h_display) && 2687 (si->ps.p2_timing.h_sync_start == si->ps.con2_screen.timing.h_sync_start) && 2688 (si->ps.p2_timing.h_sync_end == si->ps.con2_screen.timing.h_sync_end) && 2689 (si->ps.p2_timing.h_total == si->ps.con2_screen.timing.h_total) && 2690 (si->ps.p2_timing.v_display == si->ps.con2_screen.timing.v_display) && 2691 (si->ps.p2_timing.v_sync_start == si->ps.con2_screen.timing.v_sync_start) && 2692 (si->ps.p2_timing.v_sync_end == si->ps.con2_screen.timing.v_sync_end) && 2693 (si->ps.p2_timing.v_total == si->ps.con2_screen.timing.v_total)) { 2694 /* fill-out crtc2_screen from EDID info fetched from connector 2 */ 2695 memcpy(&(si->ps.crtc2_screen), &(si->ps.con2_screen), sizeof(si->ps.crtc2_screen)); 2696 } else { 2697 /* no match or no full EDID info: use the info fetched from the GPU */ 2698 si->ps.crtc2_screen.timing.pixel_clock = si->ps.p2_timing.pixel_clock; 2699 si->ps.crtc2_screen.timing.h_display = si->ps.p2_timing.h_display; 2700 si->ps.crtc2_screen.timing.h_sync_start = si->ps.p2_timing.h_sync_start; 2701 si->ps.crtc2_screen.timing.h_sync_end = si->ps.p2_timing.h_sync_end; 2702 si->ps.crtc2_screen.timing.h_total = si->ps.p2_timing.h_total; 2703 si->ps.crtc2_screen.timing.v_display = si->ps.p2_timing.v_display; 2704 si->ps.crtc2_screen.timing.v_sync_start = si->ps.p2_timing.v_sync_start; 2705 si->ps.crtc2_screen.timing.v_sync_end = si->ps.p2_timing.v_sync_end; 2706 si->ps.crtc2_screen.timing.v_total = si->ps.p2_timing.v_total; 2707 si->ps.crtc2_screen.timing.flags = si->ps.p2_timing.flags; 2708 si->ps.crtc2_screen.have_native_edid = true; 2709 si->ps.crtc2_screen.aspect = 2710 (si->ps.p2_timing.h_display / ((float)si->ps.p2_timing.v_display)); 2711 si->ps.crtc2_screen.digital = true; 2712 } 2713 } 2714 } 2715 2716 if (si->ps.card_type != NV11) 2717 { 2718 /* panels are pre-connected to a CRTC (1 or 2) by the card's BIOS, 2719 * we can't change this (lack of info) */ 2720 2721 /* detect analog monitors. First try EDID, else use load sensing. */ 2722 /* (load sensing is confirmed working OK on NV18, NV28 and NV34.) */ 2723 2724 /* secondary connector */ 2725 if (si->ps.con2_screen.have_native_edid) { 2726 if (!si->ps.con2_screen.digital) si->ps.monitors |= CRTC2_VGA; 2727 } else { 2728 if (nv_dac2_crt_connected()) { 2729 si->ps.monitors |= CRTC2_VGA; 2730 /* assume 4:3 monitor on con2 */ 2731 si->ps.con2_screen.aspect = 1.33; 2732 } 2733 } 2734 2735 /* Note: digitally connected panels take precedence over analog connected screens. */ 2736 /* fill-out crtc2_screen if not already filled in by TMDS */ 2737 if ((si->ps.monitors & (CRTC2_TMDS | CRTC2_VGA)) == CRTC2_VGA) { 2738 /* fill-out crtc2_screen from EDID info, or faked info if EDID failed. */ 2739 memcpy(&(si->ps.crtc2_screen), &(si->ps.con2_screen), sizeof(si->ps.crtc2_screen)); 2740 } 2741 /* force widescreen types if requested */ 2742 if (si->settings.force_ws) si->ps.crtc2_screen.aspect = 1.78; 2743 2744 /* setup correct output and head use */ 2745 //fixme? add TVout (only, so no CRT(s) connected) support... 2746 switch (si->ps.monitors) 2747 { 2748 case 0x00: /* no monitor found at all */ 2749 LOG(2,("INFO: head 1 has nothing connected;\n")); 2750 LOG(2,("INFO: head 2 has nothing connected:\n")); 2751 LOG(2,("INFO: defaulting to head 1 for primary use.\n")); 2752 break; 2753 case 0x01: /* digital panel on head 1, nothing on head 2 */ 2754 LOG(2,("INFO: head 1 has a digital panel;\n")); 2755 LOG(2,("INFO: head 2 has nothing connected:\n")); 2756 LOG(2,("INFO: defaulting to head 1 for primary use.\n")); 2757 break; 2758 case 0x02: /* analog panel or CRT on head 1, nothing on head 2 */ 2759 LOG(2,("INFO: head 1 has an analog panel or CRT;\n")); 2760 LOG(2,("INFO: head 2 has nothing connected:\n")); 2761 LOG(2,("INFO: defaulting to head 1 for primary use.\n")); 2762 break; 2763 case 0x03: /* both types on head 1, nothing on head 2 */ 2764 LOG(2,("INFO: head 1 has a digital panel AND an analog panel or CRT;\n")); 2765 LOG(2,("INFO: head 2 has nothing connected:\n")); 2766 LOG(2,("INFO: correcting...\n")); 2767 /* cross connect analog outputs so analog panel or CRT gets head 2 */ 2768 nv_general_output_select(true); 2769 si->ps.monitors = 0x21; 2770 /* tell head 2 it now has a screen (connected at connector 1) */ 2771 memcpy(&(si->ps.crtc2_screen), &(si->ps.con1_screen), sizeof(si->ps.crtc2_screen)); 2772 LOG(2,("INFO: head 1 has a digital panel;\n")); 2773 LOG(2,("INFO: head 2 has an analog panel or CRT:\n")); 2774 LOG(2,("INFO: defaulting to head 1 for primary use.\n")); 2775 break; 2776 case 0x10: /* nothing on head 1, digital panel on head 2 */ 2777 LOG(2,("INFO: head 1 has nothing connected;\n")); 2778 LOG(2,("INFO: head 2 has a digital panel:\n")); 2779 LOG(2,("INFO: defaulting to head 2 for primary use.\n")); 2780 si->ps.crtc2_prim = true; 2781 break; 2782 case 0x20: /* nothing on head 1, analog panel or CRT on head 2 */ 2783 if (si->ps.card_arch < NV40A) { 2784 LOG(2,("INFO: head 1 has nothing connected;\n")); 2785 LOG(2,("INFO: head 2 has an analog panel or CRT:\n")); 2786 LOG(2,("INFO: defaulting to head 2 for primary use.\n")); 2787 si->ps.crtc2_prim = true; 2788 } else { 2789 switch (si->ps.card_type) { 2790 case NV40: /* Geforce 6800 AGP was confirmed OK 'in the old days' */ 2791 case NV41: /* Geforce 6800 type as well - needs to be confirmed (guessing) */ 2792 case NV45: /* Geforce 6800 PCIe - needs to be confirmed (guessing) */ 2793 LOG(2,("INFO: head 1 has nothing connected;\n")); 2794 LOG(2,("INFO: head 2 has an analog panel or CRT:\n")); 2795 LOG(2,("INFO: defaulting to head 2 for primary use.\n")); 2796 si->ps.crtc2_prim = true; 2797 break; 2798 case NV44: 2799 /* NV44 is a special case in this situation (confirmed Geforce 6200LE): 2800 * It's hardware behaves as a NV40/41/45 but there's some unknown extra bit 2801 * which needs to be programmed now to get CRTC2/DAC2 displaying anything 2802 * else than blackness (with monitor ON @ correct refresh and resolution). 2803 * We are therefore forced to use CRTC1/DAC1 instead (as these are presetup 2804 * fully by the card's BIOS at POST in this situation). */ 2805 LOG(2,("INFO: head 1 has nothing connected;\n")); 2806 LOG(2,("INFO: head 2 has an analog panel or CRT:\n")); 2807 LOG(2,("INFO: cross-switching outputs for NV44!\n")); 2808 nv_general_output_select(true); 2809 LOG(2,("INFO: defaulting to head 1 for primary use.\n")); 2810 break; 2811 default: 2812 /* newer NV40 architecture cards contains (an) additional switch(es) 2813 * to connect a CRTC/DAC combination to a connector. The BIOSes of 2814 * these cards connect head1 to connectors 1 and 2 simultaneously if 2815 * only one VGA screen is found being on connector 2. Which is the 2816 * case here. 2817 * Confirmed on NV43, G71 and G73. */ 2818 LOG(2,("INFO: Both card outputs are connected to head 1;\n")); 2819 LOG(2,("INFO: defaulting to head 1 for primary use.\n")); 2820 break; 2821 } 2822 } 2823 break; 2824 case 0x30: /* nothing on head 1, both types on head 2 */ 2825 LOG(2,("INFO: head 1 has nothing connected;\n")); 2826 LOG(2,("INFO: head 2 has a digital panel AND an analog panel or CRT:\n")); 2827 LOG(2,("INFO: correcting...\n")); 2828 /* cross connect analog outputs so analog panel or CRT gets head 1 */ 2829 nv_general_output_select(true); 2830 si->ps.monitors = 0x12; 2831 /* tell head 1 it now has a screen (connected at connector 2) */ 2832 memcpy(&(si->ps.crtc1_screen), &(si->ps.con2_screen), sizeof(si->ps.crtc1_screen)); 2833 LOG(2,("INFO: head 1 has an analog panel or CRT;\n")); 2834 LOG(2,("INFO: head 2 has a digital panel:\n")); 2835 LOG(2,("INFO: defaulting to head 2 for primary use.\n")); 2836 si->ps.crtc2_prim = true; 2837 break; 2838 case 0x11: /* digital panels on both heads */ 2839 LOG(2,("INFO: head 1 has a digital panel;\n")); 2840 LOG(2,("INFO: head 2 has a digital panel:\n")); 2841 LOG(2,("INFO: defaulting to head 1 for primary use.\n")); 2842 break; 2843 case 0x12: /* analog panel or CRT on head 1, digital panel on head 2 */ 2844 LOG(2,("INFO: head 1 has an analog panel or CRT;\n")); 2845 LOG(2,("INFO: head 2 has a digital panel:\n")); 2846 LOG(2,("INFO: defaulting to head 2 for primary use.\n")); 2847 si->ps.crtc2_prim = true; 2848 break; 2849 case 0x21: /* digital panel on head 1, analog panel or CRT on head 2 */ 2850 LOG(2,("INFO: head 1 has a digital panel;\n")); 2851 LOG(2,("INFO: head 2 has an analog panel or CRT:\n")); 2852 LOG(2,("INFO: defaulting to head 1 for primary use.\n")); 2853 break; 2854 case 0x22: /* analog panel(s) or CRT(s) on both heads */ 2855 LOG(2,("INFO: head 1 has an analog panel or CRT;\n")); 2856 LOG(2,("INFO: head 2 has an analog panel or CRT:\n")); 2857 LOG(2,("INFO: defaulting to head 1 for primary use.\n")); 2858 break; 2859 case 0x32: /* more than two monitors connected to just two outputs: illegal! */ 2860 LOG(2,("INFO: illegal monitor setup ($%02x):\n", si->ps.monitors)); 2861 /* head 2 takes precedence because it has a digital panel while 2862 * head 1 has not. */ 2863 LOG(2,("INFO: defaulting to head 2 for primary use.\n")); 2864 si->ps.crtc2_prim = true; 2865 break; 2866 default: /* more than two monitors connected to just two outputs: illegal! */ 2867 LOG(2,("INFO: illegal monitor setup ($%02x):\n", si->ps.monitors)); 2868 LOG(2,("INFO: defaulting to head 1 for primary use.\n")); 2869 break; 2870 } 2871 } 2872 else /* dualhead NV11 cards */ 2873 { 2874 /* confirmed no analog output switch-options for NV11 */ 2875 LOG(2,("INFO: NV11 outputs are hardwired to be straight-through\n")); 2876 2877 /* (DDC or load sense analog monitor on secondary connector is impossible on NV11) */ 2878 2879 /* force widescreen types if requested */ 2880 if (si->settings.force_ws) si->ps.crtc2_screen.aspect = 1.78; 2881 2882 /* setup correct output and head use */ 2883 //fixme? add TVout (only, so no CRT(s) connected) support... 2884 switch (si->ps.monitors) 2885 { 2886 case 0x00: /* no monitor found at all */ 2887 LOG(2,("INFO: head 1 has nothing connected;\n")); 2888 LOG(2,("INFO: head 2 has nothing connected:\n")); 2889 LOG(2,("INFO: defaulting to head 1 for primary use.\n")); 2890 break; 2891 case 0x01: /* digital panel on head 1, nothing on head 2 */ 2892 LOG(2,("INFO: head 1 has a digital panel;\n")); 2893 LOG(2,("INFO: head 2 has nothing connected:\n")); 2894 LOG(2,("INFO: defaulting to head 1 for primary use.\n")); 2895 break; 2896 case 0x02: /* analog panel or CRT on head 1, nothing on head 2 */ 2897 LOG(2,("INFO: head 1 has an analog panel or CRT;\n")); 2898 LOG(2,("INFO: head 2 has nothing connected:\n")); 2899 LOG(2,("INFO: defaulting to head 1 for primary use.\n")); 2900 break; 2901 case 0x03: /* both types on head 1, nothing on head 2 */ 2902 LOG(2,("INFO: head 1 has a digital panel AND an analog panel or CRT;\n")); 2903 LOG(2,("INFO: head 2 has nothing connected:\n")); 2904 LOG(2,("INFO: correction not possible...\n")); 2905 LOG(2,("INFO: defaulting to head 1 for primary use.\n")); 2906 break; 2907 case 0x10: /* nothing on head 1, digital panel on head 2 */ 2908 LOG(2,("INFO: head 1 has nothing connected;\n")); 2909 LOG(2,("INFO: head 2 has a digital panel:\n")); 2910 LOG(2,("INFO: defaulting to head 2 for primary use.\n")); 2911 si->ps.crtc2_prim = true; 2912 break; 2913 case 0x11: /* digital panels on both heads */ 2914 LOG(2,("INFO: head 1 has a digital panel;\n")); 2915 LOG(2,("INFO: head 2 has a digital panel:\n")); 2916 LOG(2,("INFO: defaulting to head 1 for primary use.\n")); 2917 break; 2918 case 0x12: /* analog panel or CRT on head 1, digital panel on head 2 */ 2919 LOG(2,("INFO: head 1 has an analog panel or CRT;\n")); 2920 LOG(2,("INFO: head 2 has a digital panel:\n")); 2921 LOG(2,("INFO: defaulting to head 2 for primary use.\n")); 2922 si->ps.crtc2_prim = true; 2923 break; 2924 default: /* more than two monitors connected to just two outputs: illegal! */ 2925 LOG(2,("INFO: illegal monitor setup ($%02x):\n", si->ps.monitors)); 2926 LOG(2,("INFO: defaulting to head 1 for primary use.\n")); 2927 break; 2928 } 2929 } 2930 } 2931 else /* singlehead cards */ 2932 { 2933 //fixme? add TVout (only, so no CRT connected) support... 2934 } 2935} 2936 2937status_t get_crtc1_screen_native_mode(display_mode *mode) 2938{ 2939 if (!si->ps.crtc1_screen.have_native_edid) return B_ERROR; 2940 2941 mode->space = B_RGB32_LITTLE; 2942 mode->virtual_width = si->ps.crtc1_screen.timing.h_display; 2943 mode->virtual_height = si->ps.crtc1_screen.timing.v_display; 2944 mode->h_display_start = 0; 2945 mode->v_display_start = 0; 2946 mode->flags = 0; 2947 memcpy(&mode->timing, &si->ps.crtc1_screen.timing, sizeof(mode->timing)); 2948 2949 return B_OK; 2950} 2951 2952status_t get_crtc2_screen_native_mode(display_mode *mode) 2953{ 2954 if (!si->ps.crtc2_screen.have_native_edid) return B_ERROR; 2955 2956 mode->space = B_RGB32_LITTLE; 2957 mode->virtual_width = si->ps.crtc2_screen.timing.h_display; 2958 mode->virtual_height = si->ps.crtc2_screen.timing.v_display; 2959 mode->h_display_start = 0; 2960 mode->v_display_start = 0; 2961 mode->flags = 0; 2962 memcpy(&mode->timing, &si->ps.crtc2_screen.timing, sizeof(mode->timing)); 2963 2964 return B_OK; 2965} 2966 2967static void pinsnv4_fake(void) 2968{ 2969 /* we have a standard PLL */ 2970 si->ps.ext_pll = false; 2971 /* carefull not to take to high limits, and high should be >= 2x low. */ 2972 si->ps.max_system_vco = 256; 2973 si->ps.min_system_vco = 128; 2974 si->ps.max_pixel_vco = 256; 2975 si->ps.min_pixel_vco = 128; 2976 si->ps.max_video_vco = 0; 2977 si->ps.min_video_vco = 0; 2978 si->ps.max_dac1_clock = 250; 2979 si->ps.max_dac1_clock_8 = 250; 2980 si->ps.max_dac1_clock_16 = 250; 2981 /* 'failsave' values */ 2982 si->ps.max_dac1_clock_24 = 220; 2983 si->ps.max_dac1_clock_32 = 180; 2984 si->ps.max_dac1_clock_32dh = 180; 2985 /* secondary head */ 2986 si->ps.max_dac2_clock = 0; 2987 si->ps.max_dac2_clock_8 = 0; 2988 si->ps.max_dac2_clock_16 = 0; 2989 si->ps.max_dac2_clock_24 = 0; 2990 si->ps.max_dac2_clock_32 = 0; 2991 /* 'failsave' values */ 2992 si->ps.max_dac2_clock_32dh = 0; 2993 //fixme: primary & secondary_dvi should be overrule-able via nv.settings 2994 si->ps.primary_dvi = false; 2995 si->ps.secondary_dvi = false; 2996 /* not used (yet) because no coldstart will be attempted (yet) */ 2997 si->ps.std_engine_clock = 90; 2998 si->ps.std_memory_clock = 110; 2999} 3000 3001static void pinsnv5_nv5m64_fake(void) 3002{ 3003 /* we have a standard PLL */ 3004 si->ps.ext_pll = false; 3005 /* carefull not to take to high limits, and high should be >= 2x low. */ 3006 si->ps.max_system_vco = 300; 3007 si->ps.min_system_vco = 128; 3008 si->ps.max_pixel_vco = 300; 3009 si->ps.min_pixel_vco = 128; 3010 si->ps.max_video_vco = 0; 3011 si->ps.min_video_vco = 0; 3012 si->ps.max_dac1_clock = 300; 3013 si->ps.max_dac1_clock_8 = 300; 3014 si->ps.max_dac1_clock_16 = 300; 3015 /* 'failsave' values */ 3016 si->ps.max_dac1_clock_24 = 270; 3017 si->ps.max_dac1_clock_32 = 230; 3018 si->ps.max_dac1_clock_32dh = 230; 3019 /* secondary head */ 3020 si->ps.max_dac2_clock = 0; 3021 si->ps.max_dac2_clock_8 = 0; 3022 si->ps.max_dac2_clock_16 = 0; 3023 si->ps.max_dac2_clock_24 = 0; 3024 si->ps.max_dac2_clock_32 = 0; 3025 /* 'failsave' values */ 3026 si->ps.max_dac2_clock_32dh = 0; 3027 //fixme: primary & secondary_dvi should be overrule-able via nv.settings 3028 si->ps.primary_dvi = false; 3029 si->ps.secondary_dvi = false; 3030 /* not used (yet) because no coldstart will be attempted (yet) */ 3031 si->ps.std_engine_clock = 125; 3032 si->ps.std_memory_clock = 150; 3033} 3034 3035static void pinsnv6_fake(void) 3036{ 3037 /* we have a standard PLL */ 3038 si->ps.ext_pll = false; 3039 /* carefull not to take to high limits, and high should be >= 2x low. */ 3040 si->ps.max_system_vco = 300; 3041 si->ps.min_system_vco = 128; 3042 si->ps.max_pixel_vco = 300; 3043 si->ps.min_pixel_vco = 128; 3044 si->ps.max_video_vco = 0; 3045 si->ps.min_video_vco = 0; 3046 si->ps.max_dac1_clock = 300; 3047 si->ps.max_dac1_clock_8 = 300; 3048 si->ps.max_dac1_clock_16 = 300; 3049 /* 'failsave' values */ 3050 si->ps.max_dac1_clock_24 = 270; 3051 si->ps.max_dac1_clock_32 = 230; 3052 si->ps.max_dac1_clock_32dh = 230; 3053 /* secondary head */ 3054 si->ps.max_dac2_clock = 0; 3055 si->ps.max_dac2_clock_8 = 0; 3056 si->ps.max_dac2_clock_16 = 0; 3057 si->ps.max_dac2_clock_24 = 0; 3058 si->ps.max_dac2_clock_32 = 0; 3059 /* 'failsave' values */ 3060 si->ps.max_dac2_clock_32dh = 0; 3061 //fixme: primary & secondary_dvi should be overrule-able via nv.settings 3062 si->ps.primary_dvi = false; 3063 si->ps.secondary_dvi = false; 3064 /* not used (yet) because no coldstart will be attempted (yet) */ 3065 si->ps.std_engine_clock = 100; 3066 si->ps.std_memory_clock = 125; 3067} 3068 3069static void pinsnv10_arch_fake(void) 3070{ 3071 /* we have a standard PLL */ 3072 si->ps.ext_pll = false; 3073 /* carefull not to take to high limits, and high should be >= 2x low. */ 3074 si->ps.max_system_vco = 350; 3075 si->ps.min_system_vco = 128; 3076 si->ps.max_pixel_vco = 350; 3077 si->ps.min_pixel_vco = 128; 3078 si->ps.max_video_vco = 350; 3079 si->ps.min_video_vco = 128; 3080 si->ps.max_dac1_clock = 350; 3081 si->ps.max_dac1_clock_8 = 350; 3082 si->ps.max_dac1_clock_16 = 350; 3083 /* 'failsave' values */ 3084 si->ps.max_dac1_clock_24 = 320; 3085 si->ps.max_dac1_clock_32 = 280; 3086 si->ps.max_dac1_clock_32dh = 250; 3087 /* secondary head */ 3088 if (si->ps.card_type < NV17) 3089 { 3090 /* if a GeForce2 has analog VGA dualhead capability, 3091 * it uses an external secondary DAC probably with limited capability. */ 3092 /* (called twinview technology) */ 3093 si->ps.max_dac2_clock = 200; 3094 si->ps.max_dac2_clock_8 = 200; 3095 si->ps.max_dac2_clock_16 = 200; 3096 si->ps.max_dac2_clock_24 = 200; 3097 si->ps.max_dac2_clock_32 = 200; 3098 /* 'failsave' values */ 3099 si->ps.max_dac2_clock_32dh = 180; 3100 } 3101 else 3102 { 3103 /* GeForce4 cards have dual integrated DACs with identical capaability */ 3104 /* (called nview technology) */ 3105 si->ps.max_dac2_clock = 350; 3106 si->ps.max_dac2_clock_8 = 350; 3107 si->ps.max_dac2_clock_16 = 350; 3108 /* 'failsave' values */ 3109 si->ps.max_dac2_clock_24 = 320; 3110 si->ps.max_dac2_clock_32 = 280; 3111 si->ps.max_dac2_clock_32dh = 250; 3112 } 3113 //fixme: primary & secondary_dvi should be overrule-able via nv.settings 3114 si->ps.primary_dvi = false; 3115 si->ps.secondary_dvi = false; 3116 /* not used (yet) because no coldstart will be attempted (yet) */ 3117 si->ps.std_engine_clock = 120; 3118 si->ps.std_memory_clock = 150; 3119} 3120 3121static void pinsnv20_arch_fake(void) 3122{ 3123 /* we have a standard PLL */ 3124 si->ps.ext_pll = false; 3125 /* carefull not to take to high limits, and high should be >= 2x low. */ 3126 si->ps.max_system_vco = 350; 3127 si->ps.min_system_vco = 128; 3128 si->ps.max_pixel_vco = 350; 3129 si->ps.min_pixel_vco = 128; 3130 si->ps.max_video_vco = 350; 3131 si->ps.min_video_vco = 128; 3132 si->ps.max_dac1_clock = 350; 3133 si->ps.max_dac1_clock_8 = 350; 3134 si->ps.max_dac1_clock_16 = 350; 3135 /* 'failsave' values */ 3136 si->ps.max_dac1_clock_24 = 320; 3137 si->ps.max_dac1_clock_32 = 280; 3138 si->ps.max_dac1_clock_32dh = 250; 3139 /* secondary head */ 3140 /* GeForce4 cards have dual integrated DACs with identical capaability */ 3141 /* (called nview technology) */ 3142 si->ps.max_dac2_clock = 350; 3143 si->ps.max_dac2_clock_8 = 350; 3144 si->ps.max_dac2_clock_16 = 350; 3145 /* 'failsave' values */ 3146 si->ps.max_dac2_clock_24 = 320; 3147 si->ps.max_dac2_clock_32 = 280; 3148 si->ps.max_dac2_clock_32dh = 250; 3149 //fixme: primary & secondary_dvi should be overrule-able via nv.settings 3150 si->ps.primary_dvi = false; 3151 si->ps.secondary_dvi = false; 3152 /* not used (yet) because no coldstart will be attempted (yet) */ 3153 si->ps.std_engine_clock = 175; 3154 si->ps.std_memory_clock = 200; 3155} 3156 3157/* notes on PLL's: 3158 on NV34, GeForce FX 5200, id 0x0322 DAC1 PLL observed behaviour: 3159 - Fcomp may be as high as 27Mhz (BIOS), and current set range seems ok as well; 3160 - Fvco may not be as low as 216Mhz (DVI pixelclock intermittant locking error, 3161 visible as horizontal shifting picture and black screen (out of range): both intermittant); 3162 - Fvco may be as high as 432Mhz (BIOS); 3163 - This is not an extended PLL: the second divisor register does not do anything. 3164*/ 3165static void pinsnv30_arch_fake(void) 3166{ 3167 /* determine PLL type */ 3168 if ((si->ps.card_type == NV31) || 3169 (si->ps.card_type == NV36) || 3170 (si->ps.card_type >= NV40)) 3171 { 3172 /* we have a extended PLL */ 3173 si->ps.ext_pll = true; 3174 } 3175 else 3176 { 3177 /* we have a standard PLL */ 3178 si->ps.ext_pll = false; 3179 } 3180 /* carefull not to take to high limits, and high should be >= 2x low. */ 3181 si->ps.max_system_vco = 350; 3182 si->ps.min_system_vco = 128; 3183 if (si->ps.ext_pll) 3184 { 3185 si->ps.max_pixel_vco = 600; 3186 si->ps.min_pixel_vco = 220; 3187 si->ps.max_video_vco = 600; 3188 si->ps.min_video_vco = 220; 3189 } 3190 else 3191 { 3192 si->ps.max_pixel_vco = 350; 3193 si->ps.min_pixel_vco = 128; 3194 si->ps.max_video_vco = 350; 3195 si->ps.min_video_vco = 128; 3196 } 3197 si->ps.max_dac1_clock = 350; 3198 si->ps.max_dac1_clock_8 = 350; 3199 si->ps.max_dac1_clock_16 = 350; 3200 /* 'failsave' values */ 3201 si->ps.max_dac1_clock_24 = 320; 3202 si->ps.max_dac1_clock_32 = 280; 3203 si->ps.max_dac1_clock_32dh = 250; 3204 /* secondary head */ 3205 /* GeForceFX cards have dual integrated DACs with identical capability */ 3206 /* (called nview technology) */ 3207 si->ps.max_dac2_clock = 350; 3208 si->ps.max_dac2_clock_8 = 350; 3209 si->ps.max_dac2_clock_16 = 350; 3210 /* 'failsave' values */ 3211 si->ps.max_dac2_clock_24 = 320; 3212 si->ps.max_dac2_clock_32 = 280; 3213 si->ps.max_dac2_clock_32dh = 250; 3214 //fixme: primary & secondary_dvi should be overrule-able via nv.settings 3215 si->ps.primary_dvi = false; 3216 si->ps.secondary_dvi = false; 3217 /* not used (yet) because no coldstart will be attempted (yet) */ 3218 si->ps.std_engine_clock = 190; 3219 si->ps.std_memory_clock = 190; 3220 3221 if ((CFGR(DEVID) & 0xfff0ffff) == 0x024010de) { 3222 /* C51 chipset */ 3223 si->ps.max_system_vco = 1000; 3224 si->ps.min_system_vco = 500; 3225 si->ps.max_pixel_vco = 1000; 3226 si->ps.min_pixel_vco = 500; 3227 si->ps.max_video_vco = 1000; 3228 si->ps.min_video_vco = 500; 3229 } 3230} 3231 3232static void getRAMsize_arch_nv4(void) 3233{ 3234 uint32 strapinfo = NV_REG32(NV32_NV4STRAPINFO); 3235 3236 if (strapinfo & 0x00000100) 3237 { 3238 /* Unified memory architecture used */ 3239 si->ps.memory_size = 1024 * 1024 * 3240 ((((strapinfo & 0x0000f000) >> 12) * 2) + 2); 3241 3242 LOG(8,("INFO: NV4 architecture chip with UMA detected\n")); 3243 } 3244 else 3245 { 3246 /* private memory architecture used */ 3247 switch (strapinfo & 0x00000003) 3248 { 3249 case 0: 3250 si->ps.memory_size = 32 * 1024 * 1024; 3251 break; 3252 case 1: 3253 si->ps.memory_size = 4 * 1024 * 1024; 3254 break; 3255 case 2: 3256 si->ps.memory_size = 8 * 1024 * 1024; 3257 break; 3258 case 3: 3259 si->ps.memory_size = 16 * 1024 * 1024; 3260 break; 3261 } 3262 } 3263} 3264 3265static void getstrap_arch_nv4(void) 3266{ 3267 uint32 strapinfo = NV_REG32(NV32_NVSTRAPINFO2); 3268 3269 /* determine PLL reference crystal frequency */ 3270 if (strapinfo & 0x00000040) 3271 si->ps.f_ref = 14.31818; 3272 else 3273 si->ps.f_ref = 13.50000; 3274 3275 /* these cards are always singlehead */ 3276 si->ps.secondary_head = false; 3277} 3278 3279static void getRAMsize_arch_nv10_20_30_40(void) 3280{ 3281 uint32 dev_manID = CFGR(DEVID); 3282 uint32 strapinfo = NV_REG32(NV32_NV10STRAPINFO); 3283 uint32 mem_size; 3284 3285 switch (dev_manID) 3286 { 3287 case 0x01a010de: /* Nvidia GeForce2 Integrated GPU */ 3288 case 0x01f010de: /* Nvidia GeForce4 MX Integrated GPU */ 3289 /* the kerneldriver already determined the amount of RAM these cards have at 3290 * their disposal (UMA, values read from PCI config space in other device) */ 3291 LOG(8,("INFO: nVidia GPU with UMA detected\n")); 3292 break; 3293 default: 3294 LOG(8,("INFO: kerneldriver mapped %3.3fMb framebuffer memory\n", 3295 (si->ps.memory_size / (1024.0 * 1024.0)))); 3296 LOG(8,("INFO: (Memory detection) Strapinfo value is: $%08x\n", strapinfo)); 3297 3298 mem_size = (strapinfo & 0x3ff00000); 3299 if (!mem_size) { 3300 mem_size = 16 * 1024 * 1024; 3301 3302 LOG(8,("INFO: NV10/20/30 architecture chip with unknown RAM amount detected;\n")); 3303 LOG(8,("INFO: Setting 16Mb\n")); 3304 } 3305 /* don't attempt to adress memory not mapped by the kerneldriver */ 3306 if (si->ps.memory_size > mem_size) si->ps.memory_size = mem_size; 3307 } 3308} 3309 3310static void getstrap_arch_nv10_20_30_40(void) 3311{ 3312 uint32 dev_manID = CFGR(DEVID); 3313 uint32 strapinfo = NV_REG32(NV32_NVSTRAPINFO2); 3314 3315 /* determine if we have a dualhead card */ 3316 si->ps.secondary_head = false; 3317 switch (si->ps.card_type) 3318 { 3319 case NV04: 3320 case NV05: 3321 case NV05M64: 3322 case NV06: 3323 case NV10: 3324 case NV15: 3325 case NV20: 3326 break; 3327 default: 3328 if ((dev_manID & 0xfff0ffff) == 0x01a010de) 3329 { 3330 /* this is a singlehead NV11! */ 3331 } 3332 else 3333 { 3334 si->ps.secondary_head = true; 3335 } 3336 } 3337 3338 /* determine PLL reference crystal frequency: three types are used... */ 3339 if ((si->ps.secondary_head) && (si->ps.card_type != NV11)) 3340 strapinfo &= 0x00400040; 3341 else 3342 strapinfo &= 0x00000040; 3343 3344 switch (strapinfo) { 3345 case 0x00000000: 3346 si->ps.f_ref = 13.50000; 3347 break; 3348 case 0x00000040: 3349 si->ps.f_ref = 14.31818; 3350 break; 3351 case 0x00400000: 3352 si->ps.f_ref = 27.00000; 3353 break; 3354 case 0x00400040: 3355 si->ps.f_ref = 25.00000; 3356 break; 3357 } 3358} 3359 3360void dump_pins(void) 3361{ 3362 char *msg = ""; 3363 3364 LOG(2,("INFO: pinsdump follows:\n")); 3365 LOG(2,("PLL type: %s\n", si->ps.ext_pll ? "extended" : "standard")); 3366 LOG(2,("f_ref: %fMhz\n", si->ps.f_ref)); 3367 LOG(2,("max_system_vco: %dMhz\n", si->ps.max_system_vco)); 3368 LOG(2,("min_system_vco: %dMhz\n", si->ps.min_system_vco)); 3369 LOG(2,("max_pixel_vco: %dMhz\n", si->ps.max_pixel_vco)); 3370 LOG(2,("min_pixel_vco: %dMhz\n", si->ps.min_pixel_vco)); 3371 LOG(2,("max_video_vco: %dMhz\n", si->ps.max_video_vco)); 3372 LOG(2,("min_video_vco: %dMhz\n", si->ps.min_video_vco)); 3373 LOG(2,("std_engine_clock: %dMhz\n", si->ps.std_engine_clock)); 3374 LOG(2,("std_memory_clock: %dMhz\n", si->ps.std_memory_clock)); 3375 LOG(2,("max_dac1_clock: %dMhz\n", si->ps.max_dac1_clock)); 3376 LOG(2,("max_dac1_clock_8: %dMhz\n", si->ps.max_dac1_clock_8)); 3377 LOG(2,("max_dac1_clock_16: %dMhz\n", si->ps.max_dac1_clock_16)); 3378 LOG(2,("max_dac1_clock_24: %dMhz\n", si->ps.max_dac1_clock_24)); 3379 LOG(2,("max_dac1_clock_32: %dMhz\n", si->ps.max_dac1_clock_32)); 3380 LOG(2,("max_dac1_clock_32dh: %dMhz\n", si->ps.max_dac1_clock_32dh)); 3381 LOG(2,("max_dac2_clock: %dMhz\n", si->ps.max_dac2_clock)); 3382 LOG(2,("max_dac2_clock_8: %dMhz\n", si->ps.max_dac2_clock_8)); 3383 LOG(2,("max_dac2_clock_16: %dMhz\n", si->ps.max_dac2_clock_16)); 3384 LOG(2,("max_dac2_clock_24: %dMhz\n", si->ps.max_dac2_clock_24)); 3385 LOG(2,("max_dac2_clock_32: %dMhz\n", si->ps.max_dac2_clock_32)); 3386 LOG(2,("max_dac2_clock_32dh: %dMhz\n", si->ps.max_dac2_clock_32dh)); 3387 LOG(2,("secondary_head: %s\n", si->ps.secondary_head ? "present" : "absent")); 3388 LOG(2,("tvout: %s\n", si->ps.tvout ? "present" : "absent")); 3389 /* setup TVout logmessage text */ 3390 switch (si->ps.tv_encoder.type) 3391 { 3392 case NONE: 3393 msg = "No"; 3394 break; 3395 case CH7003: 3396 msg = "Chrontel CH7003"; 3397 break; 3398 case CH7004: 3399 msg = "Chrontel CH7004"; 3400 break; 3401 case CH7005: 3402 msg = "Chrontel CH7005"; 3403 break; 3404 case CH7006: 3405 msg = "Chrontel CH7006"; 3406 break; 3407 case CH7007: 3408 msg = "Chrontel CH7007"; 3409 break; 3410 case CH7008: 3411 msg = "Chrontel CH7008"; 3412 break; 3413 case SAA7102: 3414 msg = "Philips SAA7102"; 3415 break; 3416 case SAA7103: 3417 msg = "Philips SAA7103"; 3418 break; 3419 case SAA7104: 3420 msg = "Philips SAA7104"; 3421 break; 3422 case SAA7105: 3423 msg = "Philips SAA7105"; 3424 break; 3425 case BT868: 3426 msg = "Brooktree/Conexant BT868"; 3427 break; 3428 case BT869: 3429 msg = "Brooktree/Conexant BT869"; 3430 break; 3431 case CX25870: 3432 msg = "Conexant CX25870"; 3433 break; 3434 case CX25871: 3435 msg = "Conexant CX25871"; 3436 break; 3437 case NVIDIA: 3438 msg = "Nvidia internal"; 3439 break; 3440 default: 3441 msg = "Unknown"; 3442 break; 3443 } 3444 LOG(2, ("%s TV encoder detected; silicon revision is $%02x\n", 3445 msg, si->ps.tv_encoder.version)); 3446// LOG(2,("primary_dvi: ")); 3447// if (si->ps.primary_dvi) LOG(2,("present\n")); else LOG(2,("absent\n")); 3448// LOG(2,("secondary_dvi: ")); 3449// if (si->ps.secondary_dvi) LOG(2,("present\n")); else LOG(2,("absent\n")); 3450 LOG(2,("card memory_size: %3.3fMb\n", (si->ps.memory_size / (1024.0 * 1024.0)))); 3451 LOG(2,("laptop: ")); 3452 if (si->ps.laptop) LOG(2,("yes\n")); else LOG(2,("no\n")); 3453 if (si->ps.monitors & CRTC1_TMDS) 3454 { 3455 LOG(2,("found DFP (digital flatpanel) on CRTC1; CRTC1 is %s\n", 3456 si->ps.slaved_tmds1 ? "slaved" : "master")); 3457 LOG(2,("panel width: %d, height: %d, aspect ratio: %1.2f\n", 3458 si->ps.p1_timing.h_display, si->ps.p1_timing.v_display, si->ps.crtc1_screen.aspect)); 3459 } 3460 if (si->ps.monitors & CRTC2_TMDS) 3461 { 3462 LOG(2,("found DFP (digital flatpanel) on CRTC2; CRTC2 is %s\n", 3463 si->ps.slaved_tmds2 ? "slaved" : "master")); 3464 LOG(2,("panel width: %d, height: %d, aspect ratio: %1.2f\n", 3465 si->ps.p2_timing.h_display, si->ps.p2_timing.v_display, si->ps.crtc2_screen.aspect)); 3466 } 3467 LOG(2,("monitor (output devices) setup matrix: $%02x\n", si->ps.monitors)); 3468 LOG(2,("INFO: end pinsdump.\n")); 3469} 3470